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    Performance enhancement in PFET transistors comprising high-k metal gate stack by increasing dopant confinement
    1.
    发明授权
    Performance enhancement in PFET transistors comprising high-k metal gate stack by increasing dopant confinement 有权
    通过增加掺杂剂约束，包括高k金属栅极堆叠的PFET晶体管的性能增强

    公开(公告)号：US08404550B2

    公开(公告)日：2013-03-26

    申请号：US12905383

    申请日：2010-10-15

    申请人： Thilo Scheiper ,  Sven Beyer ,  Andy Wei ,  Jan Hoentschel

    发明人： Thilo Scheiper ,  Sven Beyer ,  Andy Wei ,  Jan Hoentschel

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66651

    摘要： In a P-channel transistor comprising a high-k metal gate electrode structure, a superior dopant profile may be obtained, at least in the threshold adjusting semiconductor material, such as a silicon/germanium material, by incorporating a diffusion blocking species, such as fluorine, prior to forming the threshold adjusting semiconductor material. Consequently, the drain and source extension regions may be provided with a high dopant concentration as required for obtaining the target Miller capacitance without inducing undue dopant diffusion below the threshold adjusting semiconductor material, which may otherwise result in increased leakage currents and increased risk of punch through events.

    摘要翻译： 在包含高k金属栅电极结构的P沟道晶体管中，至少在阈值调节半导体材料（例如硅/锗材料）中可以通过掺入扩散阻挡物质获得优异的掺杂剂分布，例如 在形成阈值调节半导体材料之前。 因此，漏极和源极延伸区域可以被提供有高的掺杂剂浓度，以获得目标米勒电容，而不会导致低于阈值调节半导体材料的不适当的掺杂剂扩散，否则可能导致增加的漏电流和增加的穿孔风险 事件

    ADJUSTMENT OF TRANSISTOR CHARACTERISTICS BASED ON A LATE WELL IMPLANTATION
    3.
    发明申请
    ADJUSTMENT OF TRANSISTOR CHARACTERISTICS BASED ON A LATE WELL IMPLANTATION 审中-公开
    基于较晚的植被的晶体管特性的调整

    公开(公告)号：US20110186937A1

    公开(公告)日：2011-08-04

    申请号：US12914343

    申请日：2010-10-28

    申请人： Thilo Scheiper ,  Sven Beyer ,  Jan Hoentschel ,  Andy Wei

    发明人： Thilo Scheiper ,  Sven Beyer ,  Jan Hoentschel ,  Andy Wei

    IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/8234

    CPC分类号： H01L21/823412 ,  H01L21/28088 ,  H01L21/823437 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

    摘要： A self-aligned well implantation process may be performed so as to adjust threshold voltage and/or body resistance of transistors. To this end, after removing a placeholder material of gate electrode structures, the implantation process may be performed on the basis of appropriate process parameters to obtain the desired transistor characteristics. Thereafter, any appropriate electrode metal may be filled in, thereby providing gate electrode structures having superior performance. For example, high-k metal gate electrode structures may be formed on the basis of a replacement gate approach, while the additional late well implantation may provide a high degree of flexibility in providing different transistor versions of the same basic configuration.

    摘要翻译： 可以执行自对准阱注入工艺，以便调整晶体管的阈值电压和/或体电阻。 为此，在去除栅电极结构的占位符材料之后，可以基于适当的工艺参数进行注入工艺以获得所需的晶体管特性。 此后，可以填充任何合适的电极金属，从而提供具有优异性能的栅电极结构。 例如，可以在替代栅极方法的基础上形成高k金属栅电极结构，而附加的后期阱注入可以提供相同基本配置的不同晶体管版本的高度灵活性。

    PERFORMANCE ENHANCEMENT IN PFET TRANSISTORS COMPRISING HIGH-K METAL GATE STACK BY INCREASING DOPANT CONFINEMENT
    8.
    发明申请
    PERFORMANCE ENHANCEMENT IN PFET TRANSISTORS COMPRISING HIGH-K METAL GATE STACK BY INCREASING DOPANT CONFINEMENT 有权
    通过增加DOPANT约定包含高K金属栅极堆叠的PFET晶体管的性能增强

    公开(公告)号：US20110127618A1

    公开(公告)日：2011-06-02

    申请号：US12905383

    申请日：2010-10-15

    申请人： Thilo Scheiper ,  Sven Beyer ,  Andy Wei ,  Jan Hoentschel

    发明人： Thilo Scheiper ,  Sven Beyer ,  Andy Wei ,  Jan Hoentschel

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66651

    摘要： In a P-channel transistor comprising a high-k metal gate electrode structure, a superior dopant profile may be obtained, at least in the threshold adjusting semiconductor material, such as a silicon/germanium material, by incorporating a diffusion blocking species, such as fluorine, prior to forming the threshold adjusting semiconductor material. Consequently, the drain and source extension regions may be provided with a high dopant concentration as required for obtaining the target Miller capacitance without inducing undue dopant diffusion below the threshold adjusting semiconductor material, which may otherwise result in increased leakage currents and increased risk of punch through events.

    摘要翻译： 在包含高k金属栅电极结构的P沟道晶体管中，至少在阈值调节半导体材料（例如硅/锗材料）中可以通过掺入扩散阻挡物质获得优异的掺杂剂分布，例如 在形成阈值调节半导体材料之前。 因此，漏极和源极延伸区域可以被提供有高的掺杂剂浓度，以获得目标米勒电容，而不会导致低于阈值调节半导体材料的不适当的掺杂剂扩散，否则可能导致增加的漏电流和增加的穿孔风险 事件

    Dual Cavity Etch for Embedded Stressor Regions
    9.
    发明申请
    Dual Cavity Etch for Embedded Stressor Regions 审中-公开
    嵌入式应力区域的双腔蚀刻

    公开(公告)号：US20120292637A1

    公开(公告)日：2012-11-22

    申请号：US13109134

    申请日：2011-05-17

    申请人： Sven Beyer ,  Peter Baars ,  Jan Hoentschel ,  Thilo Scheiper

    发明人： Sven Beyer ,  Peter Baars ,  Jan Hoentschel ,  Thilo Scheiper

    IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/20

    CPC分类号： H01L21/823807 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

    摘要： Generally, the present disclosure is directed to methods for forming embedded stressor regions in semiconductor devices such as transistor elements and the like. One illustrative method disclosed herein includes forming a first material in first cavities formed in a first active area adjacent to a first channel region of a semiconductor device, wherein the first material induces a first stress in the first channel region. The method also includes, among other things, forming a second material in second cavities formed in a second active area adjacent to a second channel region of the semiconductor device, wherein the second material induces a second stress in the second channel region that is of an opposite type of the first stress in the first channel region, and wherein the first and second cavities are formed during a common etch process.

    摘要翻译： 通常，本公开涉及在诸如晶体管元件等的半导体器件中形成嵌入的应力源区域的方法。 本文公开的一种说明性方法包括在与半导体器件的第一沟道区相邻的第一有源区中形成的第一空腔中形成第一材料，其中第一材料在第一沟道区域中引起第一应力。 该方法还包括在形成在与半导体器件的第二沟道区相邻的第二有源区中的第二腔中形成第二材料，其中第二材料在第二沟道区域中引起第二应力 在第一通道区域中相反类型的第一应力，并且其中第一和第二空腔在公共蚀刻工艺期间形成。