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1.发明授权Method and apparatus of using global snooping to provide cache coherence to distributed computer nodes in a single coherent system 失效使用全局监听在单一相干系统中为分布式计算机节点提供高速缓存一致性的方法和装置公开(公告)号：US06973544B2
公开(公告)日：2005-12-06
申请号：US10045927
申请日：2002-01-09
CPC分类号： G06F12/0813 , G06F12/0817
摘要： A method and apparatus for providing cache coherence in a multiprocessor system which is configured into two or more nodes with memory local to each node and a tag and address crossbar system and a data crossbar system which interconnects all nodes. The disclosure is applicable to multiprocessor computer systems which utilize system memory distributed over more than one node and snooping of data states in each node which utilizes memory local to that node. Global snooping is used to provide a single point of serialization of data tags. A central crossbar controller examines cache state tags of a given address line for all nodes simultaneously and issues an appropriate reply back to a node requesting data while generating other data requests to any other node in the system for the purpose of maintaining cache coherence and supplying the requested data. The system utilizes memory local to each node by dividing such memory into local and remote categories which are mutually exclusive for any given cache line. The disclosure provides support for a third level remote cache for each node.
摘要翻译： 一种用于在多处理器系统中提供高速缓存一致性的方法和装置，其被配置为具有每个节点本地的存储器的两个或更多个节点以及互连所有节点的标签和地址交叉开关系统以及数据交叉开关系统。 本公开适用于利用分布在多于一个节点上的系统存储器并且利用利用该节点本地的存储器的每个节点中的数据状态的窥探的多处理器计算机系统。 全局侦听用于提供数据标签的单一序列化。 中央交叉开关控制器同时检查所有节点的给定地址线的高速缓存状态标签，并向请求数据的节点发出适当的回复，同时向系统中的任何其他节点生成其他数据请求，以便保持高速缓存的一致性并提供 请求的数据。 该系统通过将这样的存储器划分为对于任何给定的高速缓存行互斥的本地和远程类别来利用每个节点本地的存储器。 本公开提供了对于每个节点的第三级远程高速缓存的支持。
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2.发明授权公开(公告)号：US06591370B1
公开(公告)日：2003-07-08
申请号：US09471939
申请日：1999-12-23
IPC分类号： G06F104
摘要： A multinode multiprocessor computer system with distributed local clocks wherein a local clock may be synchronized with other clocks in the system without affecting the operation of the other clocks. A local clock to be synchronized is reset and counts an elapsed time since the reset. Simultaneously with resetting the local clock, a clock value from a clock on a source node is stored. The clock value from the source node is copied to the node to be synchronized and added to the elapsed time. The resulting summation is then stored in the local clock to be synchronized. As a result, the local clock is synchronized to the clock on the source node. In one system embodiment, the local clock includes a dynamic register and a base register and an adder adds the two portions together to generate an output of the local clock. For a node being synchronized, the dynamic portion is reset and allowed to count the elapsed time while the base portion is loaded with a clock value copied from the source node. In another system embodiment, a clock register stores both dynamic and base portions. For a node being synchronized, the clock register is reset and allowed to count the elapsed time. The base portion from the source node is then added to the clock register and stored in the clock register.
摘要翻译： 具有分布式本地时钟的多节点多处理器计算机系统，其中本地时钟可以与系统中的其他时钟同步，而不影响其他时钟的操作。 要同步的本地时钟被复位，并对从复位开始的经过时间进行计数。 在复位本地时钟的同时，存储源节点上的时钟的时钟值。 来自源节点的时钟值被复制到待同步的节点，并将其添加到已用时间。 然后将所得到的求和存储在本地时钟中以进行同步。 因此，本地时钟与源节点上的时钟同步。 在一个系统实施例中，本地时钟包括动态寄存器和基本寄存器，并且加法器将两个部分相加在一起以产生本地时钟的输出。 对于正在同步的节点，动态部分被重置并允许对基本部分加载从源节点复制的时钟值的经过时间进行计数。 在另一系统实施例中，时钟寄存器存储动态和基本部分。 对于正在同步的节点，时钟寄存器被复位并被允许对经过的时间进行计数。 然后将来自源节点的基本部分添加到时钟寄存器并存储在时钟寄存器中。
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公开(公告)号：US07210018B2
公开(公告)日：2007-04-24
申请号：US10334855
申请日：2002-12-30
IPC分类号： G06F12/00
CPC分类号： G06F12/0815 , G06F13/1615
摘要： A multiple-stage pipeline for transaction conversion is disclosed. A method is disclosed that converts a transaction into a set of concurrently performable actions. In a first pipeline stage, the transaction is decoded into an internal protocol evaluation (PE) command, such as by utilizing a look-up table (LUT). In a second pipeline stage, an entry within a PE random access memory (RAM) is selected, based on the internal PE command. This may be accomplished by converting the internal PE command into a PE RAM base address and an associated qualifier thereof. In a third pipeline stage, the entry within the PE RAM is converted to the set of concurrently performable actions, such as based on the PE RAM base address and its associate qualifier.
摘要翻译： 公开了一种用于事务转换的多级流水线。 公开了一种将事务转换为一组可同时执行的动作的方法。 在第一流水线阶段中，事务被解码成内部协议评估（PE）命令，例如通过利用查找表（LUT）。 在第二流水线阶段中，基于内部PE命令来选择PE随机存取存储器（RAM）内的条目。 这可以通过将内部PE命令转换为PE RAM基地址及其相关限定词来实现。 在第三流水线阶段，将PE RAM内的条目转换为一组可同时执行的动作，例如基于PE RAM基地址及其相关限定符。
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公开(公告)号：US06934835B2
公开(公告)日：2005-08-23
申请号：US10045774
申请日：2002-01-09
CPC分类号： G06F9/5061
摘要： Removing building blocks from partitions to which they have been bound is disclosed. A building block of a platform is removed from a partition of the platform by first halting activity by the partition on the building block. A first partition identifier of the building block indicates the partition of the building block. The building block joined the partition in a masterless manner. The resources of the building block are withdrawn from the partition, and the building block is deauthorized from the platform.
摘要翻译： 公开了从它们所绑定的分区中移除构建块。 通过首先停止构建块上的分区的活动，从平台的分区中移除平台的构建块。 构建块的第一分区标识符指示构建块的分区。 建筑物以无畏的方式加入了分区。 构建块的资源从分区中撤出，构建块从平台中取消。
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5.发明授权Method and apparatus for maintaining an order of write operations by processors in a multiprocessor computer to maintain memory consistency 失效用于维护多处理器计算机中的处理器的写入操作顺序以维持存储器一致性的方法和装置
公开(公告)号：US5900020A
公开(公告)日：1999-05-04
申请号：US678372
申请日：1996-06-27
CPC分类号： G06F12/0828 , G06F12/0813 , G06F2212/2542
摘要： A method and apparatus for maintaining processor consistency in a multiprocessor computer such as a multinode computer system are disclosed. A processor proceeds with write operations before its previous write operations complete, while processor consistency is maintained. A write operation begins with a request by the processor to invalidate copies of the data stored in other nodes. This current invalidate request is queued while acknowledging to the processor that the request is complete even though it has not actually completed. The processor proceeds to complete the write operation by changing the data. It can then execute subsequent operations, including other write operations. The queued request, however, is not transmitted to other nodes in the computer until all previous invalidate requests by the processor are complete. This ensures that the current invalidate request will not pass a previous invalidate request. The invalidate requests are added and removed from a processor's outstanding invalidate list as they arise and are completed. An invalidate request is completed by notifying the nodes in a linked list related to the current invalidate request that data shared by the node is now invalid.
摘要翻译： 公开了一种在诸如多节点计算机系统的多处理器计算机中维持处理器一致性的方法和装置。 处理器在其先前的写入操作完成之前进行写入操作，同时保持处理器的一致性。 写入操作从处理器的请求开始，使存储在其他节点中的数据的副本无效。 该当前无效请求被排队，同时向处理器确认请求完成，即使它尚未实际完成。 处理器继续通过更改数据来完成写入操作。 然后，它可以执行后续操作，包括其他写入操作。 然而，排队的请求不会传输到计算机中的其他节点，直到处理器的所有先前的无效请求都完成为止。 这确保当前的无效请求不会通过先前的无效请求。 无效请求在处理器未完成的无效列表出现并被完成时被添加和删除。 通过通知与当前无效请求相关的链接列表中的节点，节点共享的数据现在无效，则完成无效请求。
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公开(公告)号：US07051180B2
公开(公告)日：2006-05-23
申请号：US10045796
申请日：2002-01-09
IPC分类号： G06F12/00
CPC分类号： G06F9/5061
摘要： A masterless approach binds multiprocessor building blocks to partitions of a computer system using identifiers and indicators. A number of building blocks communicate among each other to determine a partition to which each building block is to be partitioned. For each unique partition to which one or more of the building blocks is to be partitioned, the building blocks communicate among each other to determine building block uniqueness, and then each of the building blocks joins the partition. The building blocks share with one another their logical port identifiers, which uniquely identify the building block within a partition. A commit indicator of each building block indicates that the building block has committed itself to the partition and that its identifiers cannot be changed. A partition protect indicator is set by one building block of a partition, preventing changes to the commit indicators of other building blocks wishing to join the partition except by that one building block, effectively protecting the partition. Building block protect indicators protect the building blocks themselves.
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公开(公告)号：US06823498B2
公开(公告)日：2004-11-23
申请号：US10045926
申请日：2002-01-09
IPC分类号： G06F945
CPC分类号： G06F9/5061
摘要： A masterless approach for binding building blocks to partitions is disclosed. Other blocks are first sent a first physical port identifier indicating a block's physical location, and a first partition identifier indicating the block's partition. Second physical port identifiers and second partition identifiers are received from the other blocks. The first physical port identifier and the second physical port identifiers of a subset of the other blocks are then sent to the subset, the second partition identifiers of the subset being equal to the first partition identifier. The first physical port identifier and the second physical port identifiers of the subset are also received from each block of the subset. A first logical port identifier indicating the block's logical location is sent to the subset, and second logical port identifiers are received from the subset. The block joins the partition indicated by the first partition identifier.
摘要翻译： 公开了一种用于将构建块绑定到分区的无主的方法。 其他块首先被发送指示块的物理位置的第一物理端口标识符，以及指示块的分区的第一分区标识符。 从其他块接收第二物理端口标识符和第二分区标识符。 然后将其他块的子集的第一物理端口标识符和第二物理端口标识符发送到子集，子集的第二分区标识符等于第一分区标识符。 子集的第一物理端口标识符和第二物理端口标识符也从子集的每个块接收。 指示块的逻辑位置的第一逻辑端口标识符被发送到子集，并且从子集接收第二逻辑端口标识符。 该块加入由第一个分区标识符指示的分区。
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8.发明授权Hardware support for partitioning a multiprocessor system to allow distinct operating systems 失效硬件支持分区多处理器系统以允许不同的操作系统公开(公告)号：US06910108B2
公开(公告)日：2005-06-21
申请号：US10045923
申请日：2002-01-09
CPC分类号： G06F9/54 , G06F2209/541
摘要： A system and method of partitioning a multiprocessor or multinode computer system containing two or more partitions each of which contain at least three nodes or processors and a central hardware device communicating with a requestor node or processor, a target node or processor and at least one additional node or processor in the partition. The multiprocessor system architecture allows for partitioning resources to define separate subsystems capable of running different operating systems simultaneously. The method operates with the central device, a tag and address crossbar system, which transmits requests for data from the requestor node to the target node, but not to any of the additional nodes or processors which are not defined as part of a given partition. The method provides steps of assignment of definitions to physical ports with the central device corresponding with desired partitioning of resources within the system. Data processed within the system is assigned tags which themselves are related to the defined system resources allocated to one or more desired partitions within the system.
摘要翻译： 一种分割包含两个或更多个分区的多处理器或多节点计算机系统的系统和方法，每个分区包含至少三个节点或处理器以及与请求者节点或处理器通信的中央硬件设备，目标节点或处理器以及至少一个附加 分区中的节点或处理器。 多处理器系统架构允许分区资源来定义能够同时运行不同操作系统的独立子系统。 该方法与中央设备，标签和地址交叉开关系统一起工作，该系统将请求数据从请求者节点发送到目标节点，而不是任何未被定义为给定分区的一部分的附加节点或处理器。 该方法提供了将定义分配给物理端口的步骤，中央设备对应于系统内的资源的期望分区。 在系统内处理的数据被分配标签，标签本身与分配给系统内的一个或多个所需分区的定义的系统资源相关。
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公开(公告)号：US06295584B1
公开(公告)日：2001-09-25
申请号：US08920673
申请日：1997-08-29
申请人： Donald R. DeSota , Bruce M. Gilbert , Thomas D. Lovett , Robert J. Safranek , Kenneth Frank Dove
发明人： Donald R. DeSota , Bruce M. Gilbert , Thomas D. Lovett , Robert J. Safranek , Kenneth Frank Dove
IPC分类号： G06F1200
CPC分类号： G06F12/0813 , G06F12/0284
摘要： An apparatus and method is disclosed for allowing a multiprocessor computer system with shared memory distributed among multiple nodes to appear like a single-node environment. The single-node environment is implemented with a memory map that has a unique address for every memory location in the system. Overlapping address spaces in the multinode environment are also assigned unique representative addresses that are translated to actual addresses in conformance with the multinode environment. The apparatus and method allows a wide variety of operating systems to be run on the multinode environment. Additionally, industry standard BIOS and chip sets can be used.
摘要翻译： 公开了一种用于允许具有分布在多个节点之间的共享存储器的多处理器计算机系统看起来像单节点环境的装置和方法。 单节点环境使用具有系统中每个存储单元的唯一地址的存储器映射来实现。 多重节点环境中的重叠地址空间也被分配为唯一的代表地址，这些地址空间被转换为符合多节点环境的实际地址。 该装置和方法允许在多节点环境中运行各种各样的操作系统。 另外，可以使用行业标准的BIOS和芯片组。
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10.发明授权Maintaining order of write operations in a multiprocessor for memory consistency 失效维护多处理器中写入操作的顺序，以保持内存一致性公开(公告)号：US06493809B1
公开(公告)日：2002-12-10
申请号：US09493782
申请日：2000-01-28
IPC分类号： G06F1300
CPC分类号： G06F13/4243
摘要： A method of invalidating shared cache lines such as on a sharing list by issuing an invalidate acknowledgement before actually invalidating a cache line. The method is useful in multiprocessor systems such as a distributed shared memory (DSM) or non-uniform memory access (NUMA) machines that include a number of interconnected processor nodes each having local memory and caches that store copies of the same data. In such a multiprocessor system using the Scalable Content Interface (SCI) protocol, an invalidate request is sent from the head node on the sharing list to a succeeding node on the list. In response to the invalidate request, the succeeding node issues an invalidate acknowledgement before the cache line is actually invalidated. After issuing the invalidate acknowledgement, the succeeding node initiates invalidation of the cache line. The invalidate acknowledgement can take the form of a response to the head node or a forwarding of the invalidate request to the next succeeding node on the list. To maintain processor consistency, a flag is set each time an invalidate acknowledgement is sent. The flag is cleared after the invalidation of the cache line is completed. Cacheable transactions received at the succeeding node while a flag is set are delayed until the flag is cleared.
摘要翻译： 一种使共享高速缓存行无效化的方法，例如在共享列表上通过在实际使高速缓存行无效之前发出无效确认。 该方法在诸如分布式共享存储器（DSM）或非均匀存储器访问（NUMA）机器的多处理器系统中是有用的，其包括多个互连的处理器节点，每个互连处理器节点具有存储相同数据的副本的本地存储器和高速缓存。 在使用可伸缩内容接口（SCI）协议的这种多处理器系统中，将无效请求从共享列表上的头节点发送到列表上的后续节点。 响应于无效请求，后续节点在高速缓存行实际无效之前发出无效确认。 发出无效确认后，后续节点启动高速缓存行的无效。 无效确认可以采取对头节点的响应的形式或将无效请求转发到列表上的下一个后续节点。 为了保持处理器的一致性，每次发送无效确认时都会设置一个标志。 标志在高速缓存行无效完成后被清除。 在设置标志时在后续节点处接收的可缓存事务被延迟直到该标志被清除。
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