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公开(公告)号：US06295584B1
公开(公告)日：2001-09-25
申请号：US08920673
申请日：1997-08-29
申请人： Donald R. DeSota , Bruce M. Gilbert , Thomas D. Lovett , Robert J. Safranek , Kenneth Frank Dove
发明人： Donald R. DeSota , Bruce M. Gilbert , Thomas D. Lovett , Robert J. Safranek , Kenneth Frank Dove
IPC分类号： G06F1200
CPC分类号： G06F12/0813 , G06F12/0284
摘要： An apparatus and method is disclosed for allowing a multiprocessor computer system with shared memory distributed among multiple nodes to appear like a single-node environment. The single-node environment is implemented with a memory map that has a unique address for every memory location in the system. Overlapping address spaces in the multinode environment are also assigned unique representative addresses that are translated to actual addresses in conformance with the multinode environment. The apparatus and method allows a wide variety of operating systems to be run on the multinode environment. Additionally, industry standard BIOS and chip sets can be used.
摘要翻译： 公开了一种用于允许具有分布在多个节点之间的共享存储器的多处理器计算机系统看起来像单节点环境的装置和方法。 单节点环境使用具有系统中每个存储单元的唯一地址的存储器映射来实现。 多重节点环境中的重叠地址空间也被分配为唯一的代表地址，这些地址空间被转换为符合多节点环境的实际地址。 该装置和方法允许在多节点环境中运行各种各样的操作系统。 另外，可以使用行业标准的BIOS和芯片组。
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公开(公告)号：US07210018B2
公开(公告)日：2007-04-24
申请号：US10334855
申请日：2002-12-30
IPC分类号： G06F12/00
CPC分类号： G06F12/0815 , G06F13/1615
摘要： A multiple-stage pipeline for transaction conversion is disclosed. A method is disclosed that converts a transaction into a set of concurrently performable actions. In a first pipeline stage, the transaction is decoded into an internal protocol evaluation (PE) command, such as by utilizing a look-up table (LUT). In a second pipeline stage, an entry within a PE random access memory (RAM) is selected, based on the internal PE command. This may be accomplished by converting the internal PE command into a PE RAM base address and an associated qualifier thereof. In a third pipeline stage, the entry within the PE RAM is converted to the set of concurrently performable actions, such as based on the PE RAM base address and its associate qualifier.
摘要翻译： 公开了一种用于事务转换的多级流水线。 公开了一种将事务转换为一组可同时执行的动作的方法。 在第一流水线阶段中，事务被解码成内部协议评估（PE）命令，例如通过利用查找表（LUT）。 在第二流水线阶段中，基于内部PE命令来选择PE随机存取存储器（RAM）内的条目。 这可以通过将内部PE命令转换为PE RAM基地址及其相关限定词来实现。 在第三流水线阶段，将PE RAM内的条目转换为一组可同时执行的动作，例如基于PE RAM基地址及其相关限定符。
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3.发明授权Method and apparatus for maintaining an order of write operations by processors in a multiprocessor computer to maintain memory consistency 失效用于维护多处理器计算机中的处理器的写入操作顺序以维持存储器一致性的方法和装置
公开(公告)号：US5900020A
公开(公告)日：1999-05-04
申请号：US678372
申请日：1996-06-27
CPC分类号： G06F12/0828 , G06F12/0813 , G06F2212/2542
摘要： A method and apparatus for maintaining processor consistency in a multiprocessor computer such as a multinode computer system are disclosed. A processor proceeds with write operations before its previous write operations complete, while processor consistency is maintained. A write operation begins with a request by the processor to invalidate copies of the data stored in other nodes. This current invalidate request is queued while acknowledging to the processor that the request is complete even though it has not actually completed. The processor proceeds to complete the write operation by changing the data. It can then execute subsequent operations, including other write operations. The queued request, however, is not transmitted to other nodes in the computer until all previous invalidate requests by the processor are complete. This ensures that the current invalidate request will not pass a previous invalidate request. The invalidate requests are added and removed from a processor's outstanding invalidate list as they arise and are completed. An invalidate request is completed by notifying the nodes in a linked list related to the current invalidate request that data shared by the node is now invalid.
摘要翻译： 公开了一种在诸如多节点计算机系统的多处理器计算机中维持处理器一致性的方法和装置。 处理器在其先前的写入操作完成之前进行写入操作，同时保持处理器的一致性。 写入操作从处理器的请求开始，使存储在其他节点中的数据的副本无效。 该当前无效请求被排队，同时向处理器确认请求完成，即使它尚未实际完成。 处理器继续通过更改数据来完成写入操作。 然后，它可以执行后续操作，包括其他写入操作。 然而，排队的请求不会传输到计算机中的其他节点，直到处理器的所有先前的无效请求都完成为止。 这确保当前的无效请求不会通过先前的无效请求。 无效请求在处理器未完成的无效列表出现并被完成时被添加和删除。 通过通知与当前无效请求相关的链接列表中的节点，节点共享的数据现在无效，则完成无效请求。
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公开(公告)号：US07594080B2
公开(公告)日：2009-09-22
申请号：US10661802
申请日：2003-09-12
CPC分类号： G06F12/0859 , G06F12/12
摘要： The temporary storage of a memory line to be stored in a cache while waiting for another memory line to be evicted from the cache is disclosed. A method includes evicting a first memory line currently stored in the cache and storing a second memory line not currently stored in the cache in its place. While the first memory line is being evicted, such as by first being inserted into an eviction queue, the second memory line is temporarily stored in a buffer. The buffer may be a data transfer buffer (DTB). Upon eviction of the first memory line, the second memory line is moved from the buffer into the cache.
摘要翻译： 公开了在等待另一存储器线从缓存中逐出时存储在高速缓存中的存储器线的临时存储。 一种方法包括扫描当前存储在高速缓存中的第一存储器行，并将当前存储在高速缓存中的第二存储器行存储在其中。 当第一存储器线被驱逐时，例如首先插入驱逐队列中，第二存储器线暂时存储在缓冲器中。 缓冲器可以是数据传输缓冲器（DTB）。 在驱逐第一存储器线路时，第二存储器线路从缓冲器移动到高速缓存器中。
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公开(公告)号：US07194585B2
公开(公告)日：2007-03-20
申请号：US10739698
申请日：2003-12-18
IPC分类号： G06F12/00
CPC分类号： G06F12/082 , G06F12/0813
摘要： The management of transactions received by a coherency controller is disclosed. A method of an embodiment of the invention is performed by a coherency controller of a plurality of coherency controllers of a node that has a plurality of sub-nodes. The coherency controller receives a transaction from one of the sub-nodes of the node. The transaction may relate to another sub-node of the node. However, the coherency controller nevertheless processes the transaction without having to send the transaction to another coherency controller of the node, even though the sub-node from which the transaction was received is different than the sub-node to which the transaction relates. The plurality of coherency controllers is thus shared by all of the plurality of sub-nodes of the node.
摘要翻译： 披露由一致性控制器接收的事务的管理。 本发明实施例的方法由具有多个子节点的节点的多个相干性控制器的一致性控制器执行。 一致性控制器从节点的一个子节点接收事务。 该事务可以涉及节点的另一子节点。 然而，尽管接收事务的子节点与事务相关的子节点不同，但一致性控制器仍然处理该事务而不必将事务发送到该节点的另一个一致性控制器。 因此，多个相关性控制器由节点的所有多个子节点共享。
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6.发明授权Cache entry error-correcting code (ECC) based at least on cache entry data and memory address 有权至少基于高速缓存条目数据和存储器地址的高速缓存入口纠错码（ECC）公开(公告)号：US06971041B2
公开(公告)日：2005-11-29
申请号：US09683931
申请日：2002-03-04
申请人： Donald R. DeSota , Thomas D. Lovett
发明人： Donald R. DeSota , Thomas D. Lovett
CPC分类号： G06F12/0802 , G06F11/1064
摘要： Determining an error-correcting code (ECC) for a cache entry based at least on the data stored in the cache entry and the memory address at which the data is permanently stored is disclosed. A cache entry for a desired memory address is retrieved. The cache entry includes data and a stored ECC based on the data and a memory address. An ECC is determined based at least on the data of the cache entry and the desired memory address. If the ECC at least based on the cache entry data and the desired memory address equals the stored ECC, then the cache entry caches the desired memory address without error.
摘要翻译： 公开了至少基于存储在高速缓存条目中的数据和永久存储数据的存储器地址的高速缓存条目的纠错码（ECC）。 检索所需存储器地址的缓存条目。 缓存条目包括基于数据和存储器地址的数据和存储的ECC。 至少基于高速缓存条目的数据和期望的存储器地址来确定ECC。 如果ECC至少基于高速缓存条目数据和期望的存储器地址等于所存储的ECC，则高速缓存条目高速缓存期望的存储器地址而没有错误。
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公开(公告)号：US06829679B2
公开(公告)日：2004-12-07
申请号：US10007811
申请日：2001-11-09
申请人： Donald R. DeSota , Thomas D. Lovett
发明人： Donald R. DeSota , Thomas D. Lovett
IPC分类号： G06F1300
CPC分类号： G06F12/0848 , G06F12/0888
摘要： Caching memory contents differently based on the region to which the memory has been partitioned or allocated is disclosed. A first region of a first line of memory to be cached is determined. The memory has a number of regions, including the first region, over which the lines of memory, including the first line, are partitioned. Each region has a first variable having a corresponding second variable. If the first variable for any region is greater than its corresponding second variable, one such region is selected as a second region. A line from the lines of the memory currently stored in the cache and partitioned to the second region is selected as the second line. The second line is replaced with the first line in the cache, the first variable for the second region is decremented, and the first variable for the first region is incremented.
摘要翻译： 公开了基于存储器被划分或分配的区域来不同地缓存存储器内容。 确定要缓存的第一行内存的第一区域。 存储器具有多个区域，包括第一区域，在其上划分包括第一行的存储器行。 每个区域具有具有对应的第二变量的第一变量。 如果任何区域的第一变量大于其对应的第二变量，则选择一个这样的区域作为第二区域。 选择当前存储在高速缓冲存储器中并且被分割成第二区域的存储器行的行作为第二行。 第二行被缓存中的第一行替换，第二个区域的第一个变量递减，第一个区域的第一个变量增加。
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8.发明授权Maintaining order of write operations in a multiprocessor for memory consistency 失效维护多处理器中写入操作的顺序，以保持内存一致性公开(公告)号：US06493809B1
公开(公告)日：2002-12-10
申请号：US09493782
申请日：2000-01-28
IPC分类号： G06F1300
CPC分类号： G06F13/4243
摘要： A method of invalidating shared cache lines such as on a sharing list by issuing an invalidate acknowledgement before actually invalidating a cache line. The method is useful in multiprocessor systems such as a distributed shared memory (DSM) or non-uniform memory access (NUMA) machines that include a number of interconnected processor nodes each having local memory and caches that store copies of the same data. In such a multiprocessor system using the Scalable Content Interface (SCI) protocol, an invalidate request is sent from the head node on the sharing list to a succeeding node on the list. In response to the invalidate request, the succeeding node issues an invalidate acknowledgement before the cache line is actually invalidated. After issuing the invalidate acknowledgement, the succeeding node initiates invalidation of the cache line. The invalidate acknowledgement can take the form of a response to the head node or a forwarding of the invalidate request to the next succeeding node on the list. To maintain processor consistency, a flag is set each time an invalidate acknowledgement is sent. The flag is cleared after the invalidation of the cache line is completed. Cacheable transactions received at the succeeding node while a flag is set are delayed until the flag is cleared.
摘要翻译： 一种使共享高速缓存行无效化的方法，例如在共享列表上通过在实际使高速缓存行无效之前发出无效确认。 该方法在诸如分布式共享存储器（DSM）或非均匀存储器访问（NUMA）机器的多处理器系统中是有用的，其包括多个互连的处理器节点，每个互连处理器节点具有存储相同数据的副本的本地存储器和高速缓存。 在使用可伸缩内容接口（SCI）协议的这种多处理器系统中，将无效请求从共享列表上的头节点发送到列表上的后续节点。 响应于无效请求，后续节点在高速缓存行实际无效之前发出无效确认。 发出无效确认后，后续节点启动高速缓存行的无效。 无效确认可以采取对头节点的响应的形式或将无效请求转发到列表上的下一个后续节点。 为了保持处理器的一致性，每次发送无效确认时都会设置一个标志。 标志在高速缓存行无效完成后被清除。 在设置标志时在后续节点处接收的可缓存事务被延迟直到该标志被清除。
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9.发明授权Distributed shared memory system having a first node that prevents other nodes from accessing requested data until a processor on the first node controls the requested data 失效具有第一节点的分布式共享存储器系统，其防止其他节点访问所请求的数据，直到第一节点上的处理器控制所请求的数据
公开(公告)号：US06041376A
公开(公告)日：2000-03-21
申请号：US850736
申请日：1997-04-24
IPC分类号： G06F12/08 , G06F13/16 , G06F13/364
CPC分类号： G06F12/0815 , G06F13/1663 , G06F12/0813
摘要： A multiprocessor system that assures forward progress of local processor requests for data by preventing other nodes from accessing the data until the processor request is satisfied. In one aspect of the invention, the local processor requests data through a remote cache interconnect. The remote cache interconnect tells the local processor to retry its request for data at a later time, so that the remote cache interconnect has sufficient time to obtain the data from the system interconnect. When the remote cache interconnect receives the data from the system interconnect, a hold flag is set. Any requests from other nodes for the data are rejected while the hold flag is set. When the local processor issues a retry request, the data is delivered to the processor and the hold flag is cleared. Other nodes may then obtain control of the data.
摘要翻译： 一种多处理器系统，通过防止其他节点访问数据直到满足处理器请求，确保本地处理器对数据的请求的正向进展。 在本发明的一个方面，本地处理器通过远程高速缓存互连来请求数据。 远程缓存互连告诉本地处理器稍后重试其对数据的请求，使得远程高速缓存互连具有足够的时间从系统互连获取数据。 当远程缓存互连从系统互连接收数据时，设置保持标志。 来自其他节点的任何数据请求将在保持标志置1时被拒绝。 当本地处理器发出重试请求时，数据被传递给处理器，并且保持标志被清除。 其他节点可以获得数据的控制。
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10.发明授权Method and apparatus of using global snooping to provide cache coherence to distributed computer nodes in a single coherent system 失效使用全局监听在单一相干系统中为分布式计算机节点提供高速缓存一致性的方法和装置公开(公告)号：US06973544B2
公开(公告)日：2005-12-06
申请号：US10045927
申请日：2002-01-09
CPC分类号： G06F12/0813 , G06F12/0817
摘要： A method and apparatus for providing cache coherence in a multiprocessor system which is configured into two or more nodes with memory local to each node and a tag and address crossbar system and a data crossbar system which interconnects all nodes. The disclosure is applicable to multiprocessor computer systems which utilize system memory distributed over more than one node and snooping of data states in each node which utilizes memory local to that node. Global snooping is used to provide a single point of serialization of data tags. A central crossbar controller examines cache state tags of a given address line for all nodes simultaneously and issues an appropriate reply back to a node requesting data while generating other data requests to any other node in the system for the purpose of maintaining cache coherence and supplying the requested data. The system utilizes memory local to each node by dividing such memory into local and remote categories which are mutually exclusive for any given cache line. The disclosure provides support for a third level remote cache for each node.
摘要翻译： 一种用于在多处理器系统中提供高速缓存一致性的方法和装置，其被配置为具有每个节点本地的存储器的两个或更多个节点以及互连所有节点的标签和地址交叉开关系统以及数据交叉开关系统。 本公开适用于利用分布在多于一个节点上的系统存储器并且利用利用该节点本地的存储器的每个节点中的数据状态的窥探的多处理器计算机系统。 全局侦听用于提供数据标签的单一序列化。 中央交叉开关控制器同时检查所有节点的给定地址线的高速缓存状态标签，并向请求数据的节点发出适当的回复，同时向系统中的任何其他节点生成其他数据请求，以便保持高速缓存的一致性并提供 请求的数据。 该系统通过将这样的存储器划分为对于任何给定的高速缓存行互斥的本地和远程类别来利用每个节点本地的存储器。 本公开提供了对于每个节点的第三级远程高速缓存的支持。
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