公开(公告)号：US5123097A

公开(公告)日：1992-06-16

申请号：US294529

申请日：1989-01-05

申请人： Thomas F. Joyce ,  Ming T. Miu ,  Richard P. Kelly

发明人： Thomas F. Joyce ,  Ming T. Miu ,  Richard P. Kelly

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F12/0855 ,  G06F12/0804

摘要： In a data processing system in which each of the data processing units is implemented using pipeline techniques and has a cache memory unit employing a store through strategy, the time required to prepare a write instruction operand address can be substantially shorter than the time required by the execution unit to prepare the associated write instruction operand. In order to utilize the time difference, apparatus is included in the execution cache unit for storing the write instruction operand address during the preparation of the associated write instruction operand. After storing the write instruction operand address, a next address is entered in an input register of the execution cache unit. When the newly entered address is associated with a read instruction, does not conflict with the write instruction operand address, and produces a "hit" signal when applied to the execution cache unit tag directory, the read instruction is processed by the execution unit. When a second write instruction operand address is entered in the input register, the read instruction operand address conflicts with the stored write instruction operand address or the read instruction operand address results in a "miss" when applied to the execution cache tag directory unit, the address is stored in the input register until the write instruction operand has been determined and the associated write instruction has been procossed by the execution cache unit.

公开(公告)号：US4641305A

公开(公告)日：1987-02-03

申请号：US663101

申请日：1984-10-19

申请人： Thomas F. Joyce ,  Richard P. Kelly

发明人： Thomas F. Joyce ,  Richard P. Kelly

IPC分类号： G06F11/10 ,  G06F11/14

CPC分类号： G06F11/141 ,  G06F11/1008

摘要： A method and apparatus for a microinstruction controlled unit to recover from a read error in reading microinstructions from a control store. The method provides for the overlapping of the execution of a current microinstruction while the next microinstruction is being addressed and read from the control store. Execution of the current microinstruction is begun before it is known whether or not it was read without error. The apparatus provides for aborting the execution of the current microinstruction with the read error and the next microinstruction. During the aborted execution of the next microinstruction, the current microinstruction is reread from the control store and then executed while the next microinstruction is being reread. The execution of microinstructions is aborted in a manner that does not alter the state of the microinstruction controlled unit beyond the point that would inhibit the re-execution of the aborted microinstructions.

摘要翻译： 一种微指令控制单元的方法和装置，用于在从控制存储器读取微指令时从读取错误中恢复。 该方法提供当前微指令的执行的重叠，同时从控制存储器处寻址并读取下一个微指令。 在知道是否读取错误之前，开始执行当前的微指令。 该装置允许以读取错误和下一个微指令中止当前微指令的执行。 在下一个微指令的中止执行期间，当前的微指令从控制存储器重新读取，然后在重新读取下一个微指令时执行。 微指令的执行以不改变微指令控制单元的状态超出抑制重新执行中断的微指令的点的方式中止。

公开(公告)号：US5193181A

公开(公告)日：1993-03-09

申请号：US593458

申请日：1990-10-05

申请人： George J. Barlow ,  James W. Keeley ,  Richard A. Lemay ,  Jian-Kuo Shen ,  Robert V. Ledoux, deceased ,  Thomas F. Joyce ,  Richard P. Kelly ,  Robert C. Miller

发明人： George J. Barlow ,  James W. Keeley ,  Richard A. Lemay ,  Jian-Kuo Shen ,  Robert V. Ledoux, deceased ,  Thomas F. Joyce ,  Richard P. Kelly ,  Robert C. Miller

IPC分类号： G06F11/00 ,  G06F11/22

CPC分类号： G06F11/0793 ,  G06F11/0724 ,  G06F11/0766 ,  G06F11/004 ,  G06F11/2205

摘要： The pipelined central processing system (CSS) units of a multiprocessor system are tightly coupled to connect in common to a system bus for sharing main memory and input/output controllers/devices. The CSS includes several circuit boards for the different VLSI circuit chip pipelined stages and associated control circuits in addition to the bus interface unit (BIU) circuits. Each board includes one or more unusual event (UEV) detector circuits for signaling when the behavior of a stage is abnormal. The UEV fault signals from each board are collected by the BIU board. When a UEV fault is detected, the BIU board circuits prevent any further communications with the system bus and broadcasts the UEV fault signal to the other boards causing the different pipelined stages to emulate the completion of the instructions within the pipeline thereby flushing it. It is thereafter placed in a nonpipelined mode. Control circuits execute a UEV handler microcode routine which reads the contents of syndrome registers included on each board containing the UEV indicator states in addition to error signals into register file working locations. The UEV signal is then cleared enabling the BIU to resume communications with the sytem bus.

公开(公告)号：US4942547A

公开(公告)日：1990-07-17

申请号：US131246

申请日：1987-12-07

申请人： Thomas F. Joyce ,  Richard P. Kelly ,  Jian-Kuo Shen ,  Michel M. Raguin

发明人： Thomas F. Joyce ,  Richard P. Kelly ,  Jian-Kuo Shen ,  Michel M. Raguin

IPC分类号： G06F9/38

CPC分类号： G06F9/3885

摘要： A data processing system includes the functionality of a commercial instruction processor, a scientific instruction processor and a basic instruction processor integrated into a single semiconductor logic element.

摘要翻译： 数据处理系统包括商业指令处理器，科学指令处理器和集成到单个半导体逻辑元件中的基本指令处理器的功能。

公开(公告)号：US4901222A

公开(公告)日：1990-02-13

申请号：US52108

申请日：1987-05-19

申请人： Thomas F. Joyce ,  Richard P. Kelly ,  Jian-Kuo Shen

发明人： Thomas F. Joyce ,  Richard P. Kelly ,  Jian-Kuo Shen

IPC分类号： G06F9/22 ,  G06F9/30 ,  G06F9/34 ,  G06F9/38 ,  G06F11/14 ,  G06F12/10

CPC分类号： G06F9/30076 ,  G06F11/141 ,  G06F9/30134 ,  G06F9/3863

摘要： In a data processing system using a virtual memory addressing scheme, certain software instructions call for the virtual address to be stored in a base register. The virtual address stored in the base register is incremented or decremented during the read out cycle of the previous operand to address the next operand. If the operand is not in physical memory, then the contents of the base register is restored to its original value. This invention minimizes the amount of logic required to back out of a software instruction after execution has begun and is faster than checking if all resources are present before any state change is made during the execution of a software instruction.

公开(公告)号：US5148530A

公开(公告)日：1992-09-15

申请号：US403554

申请日：1989-09-06

申请人： Thomas F. Joyce ,  Richard P. Kelly ,  Jian-Kuo Shen

发明人： Thomas F. Joyce ,  Richard P. Kelly ,  Jian-Kuo Shen

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F11/14

CPC分类号： G06F9/3005 ,  G06F11/141 ,  G06F9/3863

摘要： In a data processing system using a virtual memory adressing scheme, certain software instructions call for the virtual address to be stored in a base register. The virtual address stored in the base register is incremented or decremented during the read out cycle of the previous operand to address the next operand. If the operand is not in physical memory, then the contents of the base register is restored to its original value.

摘要翻译： 在使用虚拟存储器地址方案的数据处理系统中，某些软件指令要求将虚拟地址存储在基址寄存器中。 存储在基本寄存器中的虚拟地址在前一个操作数的读出周期中递增或递减，以寻址下一个操作数。 如果操作数不在物理内存中，则基本寄存器的内容将恢复为原始值。

公开(公告)号：US4670835A

公开(公告)日：1987-06-02

申请号：US663096

申请日：1984-10-19

申请人： Richard P. Kelly ,  Thomas F. Joyce

发明人： Richard P. Kelly ,  Thomas F. Joyce

IPC分类号： G06F9/22 ,  G06F9/26 ,  G06F9/28 ,  G06F9/30

CPC分类号： G06F9/26 ,  G06F9/268 ,  G06F9/28

摘要： Apparatus that provides interrupt operation in a central processor based system wherein internal subsystems are operated via addresses generated by a next address generator in the processor and sent to control stores associated with each subsystem to thereby read out firmware instructions which are used by a controller in each subsystem to control the operations of same. When a special condition is detected in ones of the subsystems a trap signal is sent to the next address generator which responds by generating a microinstruction address to the subsystem that generated the trap signal. The subsystem responds to the microinstruction to read out a register, the contents of which indicate the status of processing in the subsystem including the special condition. The register contents are forwarded to the processor which tests same to determine the nature of the special condition and calls a microprogram the microinstructions of which are applied to the control store of the subsystem that generated the trap signal. The subsystem responds to the microinstructions to clear the special condition. Certain subsystems may alternately send a special condition indicating signal directly to the next address generator, rather than a trap signal, and responsive thereto the next address generator calls the required microprogram to be applied to the control store of the subsystem that generated the indicating signal.

摘要翻译： 在基于中央处理器的系统中提供中断操作的装置，其中内部子系统通过由处理器中的下一个地址生成器产生的地址进行操作，并被发送到控制与每个子系统相关联的存储器，从而读出由每个子系统中的控制器使用的固件指令 子系统控制相同的操作。 当在子系统的一个子系统中检测到特殊条件时，陷阱信号被发送到下一个地址发生器，该地址发生器通过产生产生陷波信号的子系统产生一个微指令地址来进行响应。 子系统响应微指令读出寄存器，其内容表示子系统中的处理状态，包括特殊条件。 寄存器内容被转发到处理器，其对其进行测试以确定特殊条件的性质，并且将微程序的微指令应用于产生陷波信号的子系统的控制存储器。 子系统响应微指令以清除特殊情况。 某些子系统可以将特殊条件指示信号直接发送到下一个地址发生器，而不是陷阱信号，并且响应于此，下一个地址发生器调用所要求的微程序，以将其应用于产生指示信号的子系统的控制存储器。

公开(公告)号：US5117491A

公开(公告)日：1992-05-26

申请号：US332258

申请日：1989-03-31

申请人： Robert V. Ledoux ,  Richard P. Kelly ,  Forrest M. Phillips

发明人： Robert V. Ledoux ,  Richard P. Kelly ,  Forrest M. Phillips

IPC分类号： G06F12/14

CPC分类号： G06F12/1491

摘要： During the execution of an instruction by an execution unit, the instruction is stored in an instruction register, the operand including its ring number is stored in a data register and the ring number developed by the Virtual Memory Management Unit is stored in a ring effective register. The instruction addresses a control store which stores a firmware word in a control store register. A firmware field is decoded to generate a plurality of ring control signals. The ring numbers from the data and ring effective registers are compared and an effective ring number is generated. Depending on the states of the secure process signal, the ring control signals and the relative value of the ring numbers, the effective ring number is binary 00 or the larger ring number.

公开(公告)号：US4407014A

公开(公告)日：1983-09-27

申请号：US194310

申请日：1980-10-06

申请人： Thomas O. Holtey ,  Richard P. Kelly ,  Daniel G. Peters

发明人： Thomas O. Holtey ,  Richard P. Kelly ,  Daniel G. Peters

IPC分类号： G06F13/42 ,  G06F3/02 ,  G06F3/04

CPC分类号： G06F13/4256

摘要： Direct connect devices such as cathode ray tube displays are coupled to a communications controller through a long cable and a flexible line adapter package. Apparatus in the controller generates a clocking signal which is applied to a Universal Synchronous Receiver Transmitter (USRT) and to the direct connect device. The USRT receives data from a microprocessor and transmits a stream of data signals synchronized to the clocking signal. The data signals and the clocking signals are received by the direct connect device. The clocking signals strobe the data signals approximately in the center of a data pulse since transmission delays for the data signals and the clocking signals are approximately equal.

摘要翻译： 诸如阴极射线管显示器的直接连接装置通过长电缆和柔性线适配器封装耦合到通信控制器。 控制器中的设备产生一个应用于通用同步接收器发射器（USRT）和直接连接设备的时钟信号。 USRT从微处理器接收数据，并发送与时钟信号同步的数据信号流。 数据信号和时钟信号由直接连接设备接收。 由于数据信号和时钟信号的传输延迟近似相等，时钟信号大致在数据脉冲的中心选通数据信号。

公开(公告)号：US3938096A

公开(公告)日：1976-02-10

申请号：US425356

申请日：1973-12-17

申请人： James L. Brown ,  Richard P. Wilder ,  Richard P. Kelly

发明人： James L. Brown ,  Richard P. Wilder ,  Richard P. Kelly

IPC分类号： G06F12/10 ,  G06F9/355 ,  G06F12/02 ,  G06F12/06 ,  G06F9/00

CPC分类号： G06F9/342 ,  G06F12/0292 ,  G06F12/0623

摘要： Computer addressing hardware and a method of address development which utilizes the concept of a segment as the unit of addressability is disclosed.The fundamental vehicle for addressing is the segment wherein an address space is defined for a process and is included as part of the controlled information of the logical processor (the collection of hardware resources and control information necessary for the execution of a process.) The address space defines a predetermined number of different segments in which instructions can access operands. Within a segment, access is by relative location to the beginning of the segment, and is computed during address development. Any attempt to access information beyond the upper bound of the segment is detected by hardware and an exception condition occurs. An instruction may access an operand either directly or indirectly via a data descriptor, wherein an address syllable in the instruction is used for reference, and specifies whether reference is direct or indirection is to be preferred. The address syllable specifies a base register which defines the segment to be referenced and an offset within the segment. The address syllable also contains a displacement from this defined base. Address development hardware obtains the absolute address of the beginning of the segment, adds to this; the offset defined in the base registers, the displacement defined by the instructions, and if required the contents of an index register. This summation produces the required absolute address.

摘要翻译： 公开了利用段的概念作为可寻址性的单元的计算机寻址硬件和地址开发方法。