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公开(公告)号：US08310021B2
公开(公告)日：2012-11-13
申请号：US12835313
申请日：2010-07-13
IPC分类号： H01L31/115
CPC分类号： H01L31/1892 , G01T3/08 , H01L31/115 , Y02E10/50
摘要： A method of manufacturing a neutron detector comprises forming a first wafer by at least forming an oxide layer on a substrate, forming an active semiconductor layer on the oxide layer, and forming an interconnect layer on the active semiconductor layer, forming at least one electrically conductive pathway extending from the interconnect layer through the active semiconductor layer and the oxide layer, forming a circuit transfer bond between the interconnect layer and a second wafer, removing the substrate of the first wafer after forming the circuit transfer bond, depositing a bond pad on the oxide layer after removing the substrate of the first wafer, wherein the bond pad is electrically connected to the electrically conductive pathway, depositing a barrier layer on the oxide layer after removing the substrate of the first wafer, and depositing a neutron conversion layer on the barrier layer after depositing the barrier layer.
摘要翻译： 制造中子检测器的方法包括：通过至少在衬底上形成氧化层来形成第一晶片，在氧化层上形成有源半导体层，以及在有源半导体层上形成互连层，形成至少一个导电 从所述互连层延伸穿过所述有源半导体层和所述氧化物层，在所述互连层和第二晶片之间形成电路转移键，在形成所述电路转移键之后移除所述第一晶片的所述衬底， 在去除第一晶片的衬底之后，其中所述接合焊盘电连接到所述导电通路，在去除所述第一晶片的衬底之后，在所述氧化物层上沉积阻挡层，以及在所述阻挡层上沉积中子转换层 沉积阻挡层后的层。
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公开(公告)号：US20120228513A1
公开(公告)日：2012-09-13
申请号：US13424269
申请日：2012-03-19
IPC分类号： G01T1/24
摘要： Neutron detection cells and corresponding methods of detecting charged particles that make efficient use of silicon area are set forth. Three types of circuit cells/arrays are described: state latching circuits, glitch generating cells, and charge loss circuits. An array of these cells, used in conjunction with a neutron conversion film, increases the area that is sensitive to a strike by a charged particle over that of an array of SRAM cells. The result is a neutron detection cell that uses less power, costs less, and is more suitable for mass production.
摘要翻译： 阐述了中子检测单元和检测有效利用硅区域的带电粒子的相应方法。 描述了三种类型的电路单元/阵列：状态锁存电路，毛刺产生单元和电荷损耗电路。 与中子转换膜结合使用的这些电池的阵列增加了带电粒子相对于SRAM单元阵列的击穿敏感的面积。 结果是中子检测电池使用更少的功率，成本更低，更适合批量生产。
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3.发明授权Integration of high performance submicron CMOS and dual-poly non-volatile memory devices using a third polysilicon layer 失效使用第三多晶硅层集成高性能亚微米CMOS和双聚合非易失性存储器件
公开(公告)号：US5340764A
公开(公告)日：1994-08-23
申请号：US20291
申请日：1993-02-19
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792 , H01L29/34
CPC分类号： H01L27/105
摘要： An apparatus and method for integrating a submicron CMOS device and a non-volatile memory, wherein a thermal oxide layer is formed over a semiconductor substrate and a two layered polysilicon non-volatile memory device formed thereon. A portion of the thermal oxide is removed by etching, a thin gate oxide and a third layer of polysilicon having a submicron depth is deposited onto the etched region. The layer of polysilicon is used as the gate for the submicron CMOS device. In so doing a submicron CMOS device may be formed without subjecting the device to the significant re-oxidation required in formation processes for dual poly non-volatile memory devices such as EPROMs and EEPROMs, and separate device optimization is achieved.
摘要翻译： 一种用于集成亚微米CMOS器件和非易失性存储器的装置和方法，其中在半导体衬底上形成热氧化物层和形成在其上的双层多晶硅非易失性存储器件。 通过蚀刻去除热氧化物的一部分，将薄的栅极氧化物和具有亚微米深度的第三多晶硅层沉积到蚀刻区域上。 多晶硅层用作亚微米CMOS器件的栅极。 在这样做时，可以形成亚微米CMOS器件，而不会使器件受到诸如EPROM和EEPROM之类的双重多元非易失性存储器件的形成过程中所需的显着的再氧化，并且实现了单独的器件优化。
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公开(公告)号：US20100200918A1
公开(公告)日：2010-08-12
申请号：US12368880
申请日：2009-02-10
申请人： Bradley J. Larsen , Todd A. Randazzo , Cheisan Yue
发明人： Bradley J. Larsen , Todd A. Randazzo , Cheisan Yue
CPC分类号： G11C11/4125 , H01L27/11 , H01L27/1108 , H01L27/1203 , H01L29/7841
摘要： A CMOS memory element comprising silicon-on-insulator MOSFET transistors is disclosed wherein at least one of the MOSFET transistors is configured such that the body of the transistor is not connected to a voltage source and is instead permitted to electrically float. Implementations of the disclosed memory element with increased immunity to errors caused by heavy ion radiation are also disclosed.
摘要翻译： 公开了一种包括绝缘体上硅MOSFET晶体管的CMOS存储元件，其中至少一个MOSFET晶体管被配置为使得晶体管的主体不连接到电压源，而是允许电浮动。 还公开了对由重离子辐射引起的误差增加的免疫性的公开的存储元件的实现。
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5.发明申请Planar Metal-Insulator-Metal Circuit Element and Method for Planar Integration of Same 审中-公开平面金属绝缘体 - 金属电路元件及其平面集成方法公开(公告)号：US20100006912A1
公开(公告)日：2010-01-14
申请号：US12368900
申请日：2009-02-10
申请人： Bradley J. Larsen , Todd A. Randazzo , Cheisan Yue
发明人： Bradley J. Larsen , Todd A. Randazzo , Cheisan Yue
CPC分类号： H01L27/1104 , G11C11/4125 , H01L21/84 , H01L23/5223 , H01L27/11 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A complementary metal-oxide-semiconductor (CMOS) static random-access-memory (SRAM) element comprising a planar metal-insulator-metal (MIM) capacitor is disclosed, and the planar MIM capacitor is electrically connected to the transistors in the CMOS memory element to reduce the effects of charged particle radiation on the CMOS memory element. Methods for immunizing a CMOS SRAM element to the effects of charged particle radiation are also disclosed, along with methods for manufacturing CMOS SRAM including planar MIM capacitors as integrated circuits.
摘要翻译： 公开了包括平面金属 - 绝缘体 - 金属（MIM）电容器的互补金属氧化物半导体（CMOS）静态随机存取存储器（SRAM）元件，并且平面MIM电容器电连接到CMOS存储器中的晶体管 元素，以减少带电粒子辐射对CMOS存储元件的影响。 还公开了将CMOS SRAM元件免受带电粒子辐射的影响的方法，以及用于制造包括平面MIM电容器作为集成电路的CMOS SRAM的方法。
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公开(公告)号：US5493142A
公开(公告)日：1996-02-20
申请号：US397584
申请日：1995-03-02
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8234 , H01L27/02 , H01L27/088 , H01L29/78 , H01L29/76
CPC分类号： H01L29/78 , H01L27/0266 , H01L29/7835 , H01L2924/0002
摘要： An apparatus providing electrostatic discharge (ESD) protection in an input/output transistor. Disposed near the gate and the surface of the substrate is a lightly doped region. A sidewall oxide layer is selectively etched to extend laterally from a gate a significant amount. The sidewall oxide layer is also etched on an opposite side of the gate and may laterally extend an appreciable amount in that direction. A heavily doped source and drain are implanted in the substrate at areas of the surface exposed by etching, the drain separated from the gate by the significant extent of sidewall oxide. Near the surface of the substrate, the drain is separated from the gate by a similar extent of the lightly doped region, which provides a resistance in series between the drain and gate for ESD protection. The source may also be separated from the gate by a lightly doped region of appreciable extent, which acts as a series resistance between the source and the gate to mitigate ESD. The extent of the sidewall oxide, and thus the lightly doped regions separating the gate from the drain and source, can be tailored to optimize ESD protection and performance characteristics for a given application by defocusing snapback conduction.
摘要翻译： 一种在输入/输出晶体管中提供静电放电（ESD）保护的装置。 设在栅极附近和衬底表面是轻掺杂区域。 选择性地蚀刻侧壁氧化物层以从栅极横向延伸大量。 侧壁氧化物层也蚀刻在栅极的相对侧上，并且可以在该方向上横向延伸明显的量。 在通过蚀刻暴露的表面的区域，在衬底中注入重掺杂的源极和漏极，漏极通过侧壁氧化物的显着程度与栅极分离。 在衬底的表面附近，漏极通过类似程度的轻掺杂区域与栅极分离，这提供了用于ESD保护的漏极和栅极之间串联的电阻。 源极还可以通过明显程度的轻掺杂区域与栅极分离，其作为源极和栅极之间的串联电阻以减轻ESD。 侧壁氧化物的范围以及因此将栅极与漏极和源极分离的轻掺杂区域可以被调整，以通过散焦快速恢复传导优化给定应用的ESD保护和性能特性。
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公开(公告)号：US08399845B2
公开(公告)日：2013-03-19
申请号：US13424269
申请日：2012-03-19
IPC分类号： G01T3/00
摘要： Neutron detection cells and corresponding methods of detecting charged particles that make efficient use of silicon area are set forth. Three types of circuit cells/arrays are described: state latching circuits, glitch generating cells, and charge loss circuits. An array of these cells, used in conjunction with a neutron conversion film, increases the area that is sensitive to a strike by a charged particle over that of an array of SRAM cells. The result is a neutron detection cell that uses less power, costs less, and is more suitable for mass production.
摘要翻译： 阐述了中子检测单元和检测有效利用硅区域的带电粒子的相应方法。 描述了三种类型的电路单元/阵列：状态锁存电路，毛刺产生单元和电荷损耗电路。 与中子转换膜结合使用的这些电池的阵列增加了带电粒子相对于SRAM单元阵列的击穿敏感的面积。 结果是中子检测电池使用更少的功率，成本更低，更适合批量生产。
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公开(公告)号：US20120012957A1
公开(公告)日：2012-01-19
申请号：US12835313
申请日：2010-07-13
IPC分类号： H01L31/115 , H01L31/18
CPC分类号： H01L31/1892 , G01T3/08 , H01L31/115 , Y02E10/50
摘要： A method of manufacturing a neutron detector comprises forming a first wafer by at least forming an oxide layer on a substrate, forming an active semiconductor layer on the oxide layer, and forming an interconnect layer on the active semiconductor layer, forming at least one electrically conductive pathway extending from the interconnect layer through the active semiconductor layer and the oxide layer, forming a circuit transfer bond between the interconnect layer and a second wafer, removing the substrate of the first wafer after forming the circuit transfer bond, depositing a bond pad on the oxide layer after removing the substrate of the first wafer, wherein the bond pad is electrically connected to the electrically conductive pathway, depositing a barrier layer on the oxide layer after removing the substrate of the first wafer, and depositing a neutron conversion layer on the barrier layer after depositing the barrier layer.
摘要翻译： 制造中子检测器的方法包括：通过至少在衬底上形成氧化层来形成第一晶片，在氧化层上形成有源半导体层，以及在有源半导体层上形成互连层，形成至少一个导电 从所述互连层延伸穿过所述有源半导体层和所述氧化物层，在所述互连层和第二晶片之间形成电路转移键，在形成所述电路转移键之后移除所述第一晶片的所述衬底， 在去除第一晶片的衬底之后，其中所述接合焊盘电连接到所述导电通路，在去除所述第一晶片的衬底之后，在所述氧化物层上沉积阻挡层，以及在所述阻挡层上沉积中子转换层 沉积阻挡层后的层。
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9.再颁专利Integration of high performance submicron CMOS and dual-poly non-volatile memory devices using a third polysilicon layer 有权使用第三多晶硅层集成高性能亚微米CMOS和双聚合非易失性存储器件
公开(公告)号：USRE36777E
公开(公告)日：2000-07-11
申请号：US167919
申请日：1998-10-07
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792 , H01L29/34
CPC分类号： H01L27/105
摘要： An apparatus and method for integrating a submicron CMOS device and a non-volatile memory, wherein a thermal oxide layer is formed over a semiconductor substrate and a two layered polysilicon non-volatile memory device formed thereon. A portion of the thermal oxide is removed by etching, a thin gate oxide and a third layer of polysilicon having a submicron depth is deposited onto the etched region. The layer of polysilicon is used as the gate for the submicron CMOS device. In so doing a submicron CMOS device may be formed without subjecting the device to the significant re-oxidation required in formation processes for dual poly non-volatile memory devices such as EPROMs and EEPROMs, and separate device optimization is achieved.
摘要翻译： 一种用于集成亚微米CMOS器件和非易失性存储器的装置和方法，其中在半导体衬底上形成热氧化物层和形成在其上的双层多晶硅非易失性存储器件。 通过蚀刻去除热氧化物的一部分，将薄的栅极氧化物和具有亚微米深度的第三多晶硅层沉积到蚀刻区域上。 多晶硅层用作亚微米CMOS器件的栅极。 在这样做时，可以形成亚微米CMOS器件，而不会使器件受到诸如EPROM和EEPROM之类的双重多元非易失性存储器件的形成过程中所需的显着的再氧化，并且实现了单独的器件优化。
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10.发明授权Single layer polysilicon EEPROM having uniform thickness gate oxide/capacitor dielectric layer 失效具有均匀厚度的栅极氧化层/电容器介质层的单层多晶硅EEPROM
公开(公告)号：US5440159A
公开(公告)日：1995-08-08
申请号：US357525
申请日：1994-12-16
IPC分类号： H01L27/115 , H01L29/788 , H01L29/68 , H01L29/78
CPC分类号： H01L27/115 , H01L29/7883
摘要： An EEPROM transistor fabricated with a single polysilicon layer. An MOS transistor is fabricated with a subsurface electrode region defined by a stripe in a first direction. A layer of thin oxide is arranged in a second stripe, perpendicular to the first stripe and a polysilicon layer, arranged in a third stripe is disposed over the second stripe of thin oxide. An adjoining parallel plate capacitor is formed by a subsurface region of the same conductivity type as the subsurface electrodes in the first stripe. An insulative second plate of thin oxide is joined to the second stripe and a third plate of the capacitor is formed by a polysilicon plate over the oxide plate. Vertical metallization stripes in the first direction may contact with some components, while parallel metal stripes in a second layer in a perpendicular direction may contact with the remaining members. The stripe geometry allows lateral and vertical four-way symmetry for implementation of a large number of memory storage cells on a chip or wafer.
摘要翻译： 用单个多晶硅层制造的EEPROM晶体管。 制造MOS晶体管，其具有在第一方向上由条纹限定的地下电极区域。 薄层氧化物布置在垂直于第一条纹的第二条纹中，并且布置在第三条纹中的多晶硅层设置在第二条薄薄氧化物上。 邻接的平行平板电容器由与第一条纹中的地下电极相同的导电类型的地下区域形成。 薄氧化物的绝缘性第二板与第二条带接合，电容器的第三板由氧化物板上的多晶硅板形成。 在第一方向上的垂直金属化条纹可以与一些部件接触，而在第二层中垂直方向上的平行金属条可以与其余部件接触。 条纹几何形状允许横向和垂直四向对称，用于在芯片或晶片上实现大量存储器存储单元。
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