公开(公告)号：US20240404829A1

公开(公告)日：2024-12-05

申请号：US18203975

申请日：2023-05-31

Applicant: Tokyo Electron Limited

Inventor： Katie LUTKER-LEE ,  Eric Chih-Fang LIU

IPC: H01L21/033 ,  H01L21/308 ,  H01L21/311

Abstract: The present disclosure relates to methods and structures of increasing stability of soft or organic features. The methods disclosed herein may include lining soft/organic features with a lining material, depositing a lining material on the soft/organic features, or otherwise fabricating a lining structure. This provides mechanical support for the soft/organic features, thereby increasing stability of the soft/organic features. The methods, structures, and techniques described herein provide mechanical support for a soft/organic feature, thereby enabling better pattern transfer through semiconductor device fabrication processes, especially at reduced pitch and increased aspect ratio. A method for fabricating semiconductor devices may include spin-coating a patternable material on a substrate, patterning the patternable material to form a pattern including one or more protruding structures, and lining sidewalls of each of the one or more protruding structures with a silicon-containing material.

公开(公告)号：US20250138429A1

公开(公告)日：2025-05-01

申请号：US18498698

申请日：2023-10-31

Applicant: Tokyo Electron Limited

Inventor： Qi WANG ,  Steven GRZESKOWIAK ,  Nicholas SMIESZEK ,  Blaze MESSER ,  Sergey VORONIN ,  Akiteru KO ,  Eric Chih-Fang LIU ,  Ashawaraya SHALINI ,  Da SONG

IPC: G03F7/36 ,  G03F7/004 ,  H01L21/66

Abstract: A method of endpoint detection includes performing a surface treatment on a wafer without plasma in a process chamber which includes an outlet configured to output an exhaust gas of the surface treatment. An exhaust plasma is generated from the exhaust gas in a plasma coupler. The exhaust plasma is analyzed to determine an endpoint of the surface treatment. A system includes a process chamber configured to receive a wafer and perform a surface treatment on the wafer without plasma. The process chamber includes an outlet configured to output an exhaust gas of the surface treatment. A plasma coupler is configured to receive the exhaust gas and generate an exhaust plasma therefrom. A detector is configured to receive and analyze the exhaust plasma.

公开(公告)号：US20250013153A1

公开(公告)日：2025-01-09

申请号：US18347634

申请日：2023-07-06

Applicant: Tokyo Electron Limited

Inventor： Lior HULI ,  Eric Chih-Fang LIU

IPC: G03F7/11 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213

Abstract: A method of microfabrication includes forming a sacrificial layer over a film. A resist layer is formed over the sacrificial layer. The resist layer includes an extreme ultraviolet (EUV) resist. A pattern is formed in the resist layer by an EUV exposure and a wet etch followed by rinsing and drying, resulting in uncovered portions of the sacrificial layer. The uncovered portions of the sacrificial layer are treated. The pattern is transferred from the resist layer to the film by performing an etch process.

公开(公告)号：US20240304500A1

公开(公告)日：2024-09-12

申请号：US18178665

申请日：2023-03-06

Applicant: Tokyo Electron Limited

Inventor： Eric Chih-Fang LIU ,  Subhadeep KAL ,  Kai-Hung YU ,  Shihsheng CHANG

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L21/823864 ,  H01L21/823807 ,  H01L27/0924 ,  H01L29/66545

Abstract: Aspects of the present disclosure provide a method for fabricating a forksheet semiconductor structure. For example, the method can include forming on a substrate a multi-layer stack including first and second semiconductor layers stacked over one another alternately, forming a cap layer over the multi-layer stack, forming a mandrel structure from the multi-layer stack and the cap layer, forming a fill material that surrounds the mandrel structure and has a top surface level with a top of the mandrel structure, partially recessing the cap layer to uncover opposite inner sidewalls of the fill material, forming sidewall spacers on the opposite inner sidewalls, directionally etching the multi-layer stack to define an insulation wall trench using the sidewall spacers as an etch mask, and forming an insulation material within the insulation wall trench to form an insulation wall that separates the multi-layer stack into insulated first and second multi-layer stacks.

公开(公告)号：US20230352343A1

公开(公告)日：2023-11-02

申请号：US18308230

申请日：2023-04-27

Applicant: Tokyo Electron Limited

Inventor： Jeffrey SMITH ,  David POWER ,  Eric Chih-Fang LIU ,  Anton J. DEVILLIERS ,  Kandabara TAPILY ,  Jodi GRZESKOWIAK ,  David CONKLIN ,  Michael MURPHY

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/033 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L21/76816 ,  H01L21/31144 ,  H01L21/0337 ,  H01L21/76811 ,  H01L23/5226

Abstract: A process includes forming, over a dielectric layer, a hardmask stack including a first layer below a second layer below a third layer below a fourth layer. The first and third layers include a different hardmask material from the second and fourth layers. A trench pattern including sidewall spacer structures is formed over the hardmask stack. The fourth layer is etched in a first region. The fourth and third layers are etched in a second region. The fourth and third layers are etched in a third region. The fourth layer is etched in a fourth region. The second and first layers are etched in the second and third regions. The third layer is etched in the first and fourth regions. In the dielectric layer, trenches are formed in the first and fourth regions, and via openings, deeper than the trenches, are formed in the second and third regions.

公开(公告)号：US20250098277A1

公开(公告)日：2025-03-20

申请号：US18370835

申请日：2023-09-20

Applicant: Tokyo Electron Limited

Inventor： Eric Chih-Fang LIU

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method for fabricating semiconductor devices includes forming an opening. The method includes forming a blanket layer along vertical sidewalls of the opening. The method includes etching through the first recess through a first source/drain structure of the first semiconductor channel. The method includes filling the first recess with a dielectric material. The method includes removing the blanket layer between the dielectric material and the sidewall, to define a second and third recess opposite the dielectric material. The method includes etching the surface of the semiconductor device to define a fourth recess above a second source/drain structure of the first semiconductor channel. The method includes extending the third and fourth recesses through the first and second source/drain structures of the first semiconductor channel, to a first and second source/drain structure of the second semiconductor channel.

公开(公告)号：US20240405022A1

公开(公告)日：2024-12-05

申请号：US18204081

申请日：2023-05-31

Applicant: Tokyo Electron Limited

Inventor： Eric Chih-Fang LIU ,  Subhadeep KAL ,  Peter WANG ,  Ying TRICKETT ,  Ya-Ming CHEN

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/161

Abstract: A method for fabricating semiconductor devices is disclosed. The method includes forming a first fin structure and a second fin structure in a first region and a second region of a substrate, respectively, wherein the first and second fin structure and the substrate comprise a first semiconductor material; forming a first liner structure and a second liner structure at least extending along sidewalls of the first fin structure and sidewalls of the second fin structure, respectively; replacing an upper portion of the second fin structure with a second semiconductor material, while leaving the first fin structure substantially intact; and exposing a top surface and upper sidewalls of the first fin structure, and a top surface and upper sidewalls of the second fin structure.

公开(公告)号：US20220359718A1

公开(公告)日：2022-11-10

申请号：US17721551

申请日：2022-04-15

Applicant: Tokyo Electron Limited

Inventor： Yun HAN ,  Eric Chih-Fang LIU ,  Kai-Hung YU ,  Shihsheng CHANG ,  Alok RANJAN

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/311

Abstract: A method including providing a substrate including metal gate stacks and source/drain contact regions in alternating arrangement along a surface of the substrate, each of the source/drain contact regions being recessed within a respective opening between adjacent metal gate stacks such that source/drain contact regions provide a bottom of the opening and adjacent metal gate stacks provide sidewalls, and a dielectric covering the substrate such that the dielectric fills each opening. The substrate is exposed to an initial plasma etch process to remove a first portion of the dielectric from each opening down to a first depth, and a sacrificial gate capping layer is formed on the substrate while leaving each of the openings uncovered. The substrate is exposed to another plasma etch process to remove the sacrificial gate capping layer while removing a second portion of the dielectric from each opening down to a second depth.