Method of plasmonic crystal
    8.
    发明授权
    Method of plasmonic crystal 失效
    等离子体晶体的方法

    公开(公告)号:US08372476B2

    公开(公告)日:2013-02-12

    申请号:US12538936

    申请日:2009-08-11

    IPC分类号: B05D5/06

    摘要: A method of designing a plasmonic crystal is provided. The method includes: determining an arrangement period of a plasmonic crystal formed on a metal surface at an interface between a dielectric and the metal in accordance with a dispersion relation of a surface plasmon polariton at the interface and a Bragg reflection condition of the surface plasmon polariton.

    摘要翻译: 提供了一种设计等离子体晶体的方法。 该方法包括:根据表面等离子体激元在界面处的分散关系和表面等离子体激元的布拉格反射条件,确定在电介质和金属之间的界面处的金属表面上形成的等离子体晶体的排列周期 。

    DESIGN METHOD OF PLASMONIC CRYSTAL
    9.
    发明申请
    DESIGN METHOD OF PLASMONIC CRYSTAL 失效
    PLASMONIC CRYSTAL的设计方法

    公开(公告)号:US20090297693A1

    公开(公告)日:2009-12-03

    申请号:US12538936

    申请日:2009-08-11

    IPC分类号: B05D5/06

    摘要: A method of designing a plasmonic crystal is provided. The method includes: determining an arrangement period of a plasmonic crystal formed on a metal surface at an interface between a dielectric and the metal in accordance with a dispersion relation of a surface plasmon polariton at the interface and a Bragg reflection condition of the surface plasmon polariton.

    摘要翻译: 提供了一种设计等离子体晶体的方法。 该方法包括:根据表面等离子体激元在界面处的分散关系和表面等离子体激元的布拉格反射条件,确定在电介质和金属之间的界面处的金属表面上形成的等离子体晶体的排列周期 。

    Layout design apparatus and layout design method
    10.
    发明授权
    Layout design apparatus and layout design method 失效
    布局设计和布局设计方法

    公开(公告)号:US08689167B2

    公开(公告)日:2014-04-01

    申请号:US13534141

    申请日:2012-06-27

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5072 G06F17/5077

    摘要: A layout design apparatus includes: a memory unit to store design data of a hierarchical layout of a multilayer circuit including a macro; a channel count calculation unit to calculate a channel count of channels available to lead wiring from a terminal of the macro to a wiring layer based on the design data stored in the memory unit; and a path calculation unit to calculate a path for leading wiring from a terminal of the macro to the wiring layer in ascending order of the channel count.

    摘要翻译: 布局设计装置包括:存储单元,用于存储包括宏的多层电路的分层布局的设计数据; 通道计数计算单元,用于基于存储在存储单元中的设计数据,计算可用于从布线端子引导布线的通道的通道数; 以及路径计算单元,以通道数的升序来计算从宏的端子到布线层的引线的路径。