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公开(公告)号：US20110309439A1
公开(公告)日：2011-12-22
申请号：US13052254
申请日：2011-03-21
申请人： Tomoko Matsudai , Koichi Endo , Kumiko Sato , Norio Yasuhara
发明人： Tomoko Matsudai , Koichi Endo , Kumiko Sato , Norio Yasuhara
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66659 , H01L21/26586 , H01L29/0623 , H01L29/1045 , H01L29/7835
摘要： According to one embodiment, a semiconductor device includes a semiconductor substrate, a first conductivity-type region, a second conductivity-type source region, a gate insulating film and a gate electrode. The first conductivity-type region is provided in an upper layer portion of the semiconductor substrate. The second conductivity-type source region and a second conductivity-type drain region are arranged by being separated from each other in an upper layer portion of the first conductivity-type region. The gate insulating film is provided on the semiconductor substrate. The gate electrode is provided on the gate insulating film. An effective concentration of impurities in a channel region corresponding to a region directly below the gate electrode in the first conductivity-type region has a maximum at an interface between the gate insulating film and the channel region, and decreases toward a lower part of the channel region.
摘要翻译： 根据一个实施例，半导体器件包括半导体衬底，第一导电类型区域，第二导电型源极区域，栅极绝缘膜和栅极电极。 第一导电型区域设置在半导体衬底的上层部分中。 第二导电型源极区域和第二导电型漏极区域通过在第一导电类型区域的上层部分中彼此分离而布置。 栅极绝缘膜设置在半导体衬底上。 栅电极设置在栅极绝缘膜上。 与第一导电型区域中的栅电极正下方的区域对应的沟道区域中的杂质的有效浓度在栅极绝缘膜与沟道区域之间的界面处具有最大值，并且朝向沟道的下部逐渐减小 地区。
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2.发明授权MOSFET semiconductor device with backgate layer and reduced on-resistance 失效具有背栅层和降低导通电阻的MOSFET半导体器件公开(公告)号：US08362554B2
公开(公告)日：2013-01-29
申请号：US12878979
申请日：2010-09-09
申请人： Tomoko Matsudai , Norio Yasuhara , Takashi Tsurugai , Kumiko Sato
发明人： Tomoko Matsudai , Norio Yasuhara , Takashi Tsurugai , Kumiko Sato
IPC分类号： H01L29/78
CPC分类号： H01L29/0692 , H01L29/1087 , H01L29/66659 , H01L29/7835
摘要： According to one embodiment, a semiconductor device includes a drain region, a source region, a channel region, an insulating film, a gate electrode, a first semiconductor region, and a second semiconductor region. The source region includes a source layer of the first conductivity type, a first back gate layer of the second conductivity type, and a second back gate layer of the second conductivity type. The first back gate layer is adjacent to the second semiconductor region on one side in a channel length direction, and is adjacent to the source layer on one other side in the channel length direction. The second back gate layer is adjacent to the source layer on the one side in the channel length direction, and is adjacent to the second semiconductor region on the one other side in the channel length direction.
摘要翻译： 根据一个实施例，半导体器件包括漏极区，源极区，沟道区，绝缘膜，栅电极，第一半导体区和第二半导体区。 源极区包括第一导电类型的源极层，第二导电类型的第一背栅极层和第二导电类型的第二背栅极层。 第一背栅层在沟道长度方向的一侧与第二半导体区相邻，并且在沟道长度方向的另一侧与源极相邻。 第二背栅层在沟道长度方向的一侧与源极层相邻，并且与沟道长度方向的另一侧的第二半导体区域相邻。
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公开(公告)号：US20110095369A1
公开(公告)日：2011-04-28
申请号：US12878979
申请日：2010-09-09
申请人： Tomoko Matsudai , Norio Yasuhara , Takashi Tsurugai , Kumiko Sato
发明人： Tomoko Matsudai , Norio Yasuhara , Takashi Tsurugai , Kumiko Sato
IPC分类号： H01L29/772
CPC分类号： H01L29/0692 , H01L29/1087 , H01L29/66659 , H01L29/7835
摘要： According to one embodiment, a semiconductor device includes a drain region, a source region, a channel region, an insulating film, a gate electrode, a first semiconductor region, and a second semiconductor region. The source region includes a source layer of the first conductivity type, a first back gate layer of the second conductivity type, and a second back gate layer of the second conductivity type. The first back gate layer is adjacent to the second semiconductor region on one side in a channel length direction, and is adjacent to the source layer on one other side in the channel length direction. The second back gate layer is adjacent to the source layer on the one side in the channel length direction, and is adjacent to the second semiconductor region on the one other side in the channel length direction.
摘要翻译： 根据一个实施例，半导体器件包括漏极区，源极区，沟道区，绝缘膜，栅电极，第一半导体区和第二半导体区。 源极区包括第一导电类型的源极层，第二导电类型的第一背栅极层和第二导电类型的第二背栅极层。 第一背栅层在沟道长度方向的一侧与第二半导体区相邻，并且在沟道长度方向的另一侧与源极相邻。 第二背栅层在沟道长度方向的一侧与源极层相邻，并且与沟道长度方向的另一侧的第二半导体区域相邻。
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4.发明授权Semiconductor device including field effect transistor for use as a high-speed switching device and a power device 有权包括用作高速开关装置的场效应晶体管和功率器件的半导体装置公开(公告)号：US08502309B2
公开(公告)日：2013-08-06
申请号：US12645072
申请日：2009-12-22
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/119
CPC分类号： H01L29/0847 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： A body layer of a first conductivity type is formed on a semiconductor substrate, and a source layer of a second conductivity type is formed in a surface region of the body layer. An offset layer of the second conductivity type is formed on the semiconductor substrate, and a drain layer of the second conductivity type is formed in a surface region of the offset layer. An insulating film is embedded in a trench formed in the surface region of the offset layer between the source layer and the drain layer. A gate insulating film is formed on the body layer and the offset layer between the source layer and the insulating film. A gate electrode is formed on the gate insulating film. A first peak of an impurity concentration profile in the offset layer is formed at a position deeper than the insulating film.
摘要翻译： 在半导体衬底上形成第一导电类型的主体层，并且在主体层的表面区域中形成第二导电类型的源极层。 第二导电类型的偏移层形成在半导体衬底上，并且第二导电类型的漏极层形成在偏移层的表面区域中。 绝缘膜嵌入形成在源极层和漏极层之间的偏移层的表面区域中的沟槽中。 在主体层和源极层与绝缘膜之间的偏移层上形成栅极绝缘膜。 在栅极绝缘膜上形成栅电极。 偏移层中的杂质浓度分布的第一峰形成在比绝缘膜更深的位置。
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5.发明授权公开(公告)号：US07998849B2
公开(公告)日：2011-08-16
申请号：US12716352
申请日：2010-03-03
IPC分类号： H01L21/336
CPC分类号： H01L29/1045 , H01L21/26586 , H01L29/1083 , H01L29/1087 , H01L29/66659 , H01L29/7835 , H01L29/7838
摘要： A low resistance layer is formed on a semiconductor substrate, and a high resistance layer formed on the low resistance layer. A source region of a first conductivity type is formed on a surface region of the high resistance layer. A drain region of the first conductivity type is formed at a distance from the source region. A first resurf region of the first conductivity type is formed in a surface region of the high resistance layer between the source region and the drain region. A channel region of a second conductivity type is formed between the source region and the first resurf region. A gate insulating film is formed on the channel region, and a gate electrode formed on the gate insulating film. An impurity concentration in the channel region under the gate electrode gradually lowers from the source region toward the first resurf region.
摘要翻译： 在半导体衬底上形成低电阻层，形成在低电阻层上的高电阻层。 第一导电类型的源区形成在高电阻层的表面区域上。 第一导电类型的漏极区域形成在与源极区域一定距离处。 在源极区域和漏极区域之间的高电阻层的表面区域中形成第一导电类型的第一再结晶区域。 在源极区域和第一再结晶区域之间形成第二导电类型的沟道区域。 栅极绝缘膜形成在沟道区上，栅极形成在栅极绝缘膜上。 栅电极下方的沟道区域中的杂质浓度从源极区域朝向第一再结晶区域逐渐降低。
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6.发明授权Semiconductor device including field effect transistor for use as a high-speed switching device and a power device 失效包括用作高速开关装置的场效应晶体管和功率器件的半导体装置公开(公告)号：US07646059B2
公开(公告)日：2010-01-12
申请号：US11501715
申请日：2006-08-10
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/119
CPC分类号： H01L29/0847 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： A body layer of a first conductivity type is formed on a semiconductor substrate, and a source layer of a second conductivity type is formed in a surface region of the body layer. An offset layer of the second conductivity type is formed on the semiconductor substrate, and a drain layer of the second conductivity type is formed in a surface region of the offset layer. An insulating film is embedded in a trench formed in the surface region of the offset layer between the source layer and the drain layer. A gate insulating film is formed on the body layer and the offset layer between the source layer and the insulating film. A gate electrode is formed on the gate insulating film. A first peak of an impurity concentration profile in the offset layer is formed at a position deeper than the insulating film.
摘要翻译： 在半导体衬底上形成第一导电类型的主体层，并且在主体层的表面区域中形成第二导电类型的源极层。 第二导电类型的偏移层形成在半导体衬底上，并且第二导电类型的漏极层形成在偏移层的表面区域中。 绝缘膜嵌入形成在源极层和漏极层之间的偏移层的表面区域中的沟槽中。 在主体层和源极层与绝缘膜之间的偏移层上形成栅极绝缘膜。 在栅极绝缘膜上形成栅电极。 偏移层中的杂质浓度分布的第一峰形成在比绝缘膜更深的位置。
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7.发明授权Semiconductor device including power MOS field-effect transistor and driver circuit driving thereof 失效包括功率MOS场效应晶体管和其驱动电路驱动的半导体器件公开(公告)号：US07579669B2
公开(公告)日：2009-08-25
申请号：US11549297
申请日：2006-10-16
IPC分类号： H01L27/00
CPC分类号： H02M3/158 , H01L27/0922 , H01L29/41758 , H01L29/41775 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/7813 , H01L29/7835 , H01L2924/0002 , H02M1/08 , H02M7/003 , H01L2924/00
摘要： A semiconductor device comprises a high side switching element, a driver circuit, and a low side switching element. The high side switching element is formed on a first semiconductor substrate, has a current path to one end of which an input voltage is supplied, and the other end of the current path is connected to an inductance. The driver circuit is formed on the first semiconductor substrate, on which the high side switching element is formed, and drives the high side switching element. The low side switching element is formed on a second semiconductor substrate separate from the first semiconductor substrate, and has a drain connected to the inductance and a source supplied with a reference potential.
摘要翻译： 半导体器件包括高侧开关元件，驱动电路和低侧开关元件。 高侧开关元件形成在第一半导体基板上，其一端具有输入电压的电流通路，电流路径的另一端与电感连接。 驱动电路形成在形成有高侧开关元件的第一半导体基板上，驱动高侧开关元件。 低侧开关元件形成在与第一半导体衬底分离的第二半导体衬底上，并且具有连接到电感的漏极和被提供参考电位的源极。
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8.发明申请公开(公告)号：US20070040216A1
公开(公告)日：2007-02-22
申请号：US11505337
申请日：2006-08-17
IPC分类号： H01L29/76
CPC分类号： H01L29/1045 , H01L21/26586 , H01L29/1083 , H01L29/1087 , H01L29/66659 , H01L29/7835 , H01L29/7838
摘要： A low resistance layer is formed on a semiconductor substrate, and a high resistance layer formed on the low resistance layer. A source region of a first conductivity type is formed on a surface region of the high resistance layer. A drain region of the first conductivity type is formed at a distance from the source region. A first resurf region of the first conductivity type is formed in a surface region of the high resistance layer between the source region and the drain region. A channel region of a second conductivity type is formed between the source region and the first resurf region. A gate insulating film is formed on the channel region, and a gate electrode formed on the gate insulating film. An impurity concentration in the channel region under the gate electrode gradually lowers from the source region toward the first resurf region.
摘要翻译： 在半导体衬底上形成低电阻层，形成在低电阻层上的高电阻层。 第一导电类型的源区形成在高电阻层的表面区域上。 第一导电类型的漏极区域形成在与源极区域一定距离处。 在源极区域和漏极区域之间的高电阻层的表面区域中形成第一导电类型的第一再结晶区域。 在源极区域和第一再结晶区域之间形成第二导电类型的沟道区域。 栅极绝缘膜形成在沟道区上，栅极形成在栅极绝缘膜上。 栅电极下方的沟道区域中的杂质浓度从源极区域朝向第一再结晶区域逐渐降低。
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9.发明授权公开(公告)号：US07138698B2
公开(公告)日：2006-11-21
申请号：US11007254
申请日：2004-12-09
IPC分类号： H01L23/58
CPC分类号： H02M3/158 , H01L27/0922 , H01L29/41758 , H01L29/41775 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/7813 , H01L29/7835 , H01L2924/0002 , H02M1/08 , H02M7/003 , H01L2924/00
摘要： A semiconductor device comprises a high side switching element, a driver circuit, and a low side switching element. The high side switching element is formed on a first semiconductor substrate, has a current path to one end of which an input voltage is supplied, and the other end of the current path is connected to an inductance. The driver circuit is formed on the first semiconductor substrate, on which the high side switching element is formed, and drives the high side switching element. The low side switching element is formed on a second semiconductor substrate separate from the first semiconductor substrate, and has a drain connected to the inductance and a source supplied with a reference potential.
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公开(公告)号：US5751022A
公开(公告)日：1998-05-12
申请号：US806153
申请日：1997-02-25
IPC分类号： H01L29/74 , H01L29/745 , H01L29/749 , H01L31/111
CPC分类号： H01L29/749 , H01L29/7412 , H01L29/7436 , H01L29/7455
摘要： A semiconductor device is disclosed having a thyristor region coupled to a semiconductor switching device and a semiconductor rectifier. During turn-off operation, holes are drained from the p-type base region of the thyristor region through the semiconductor rectifier and to the cathode of the thyristor. During turn-on, electrons are supplied to an n-type emitter region of the thyristor from the cathode electrode through the semiconductor switching device.
摘要翻译： 公开了具有耦合到半导体开关器件和半导体整流器的晶闸管区域的半导体器件。 在关断操作期间，从晶闸管区域的p型基极区域通过半导体整流器和晶闸管的阴极排出孔。 在导通期间，电子通过半导体开关器件从阴极电极提供给晶闸管的n型发射极区域。
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