公开(公告)号：US08664692B2

公开(公告)日：2014-03-04

申请号：US13600097

申请日：2012-08-30

申请人： Tsuneo Ogura ,  Tomoko Matsudai ,  Yuichi Oshino

发明人： Tsuneo Ogura ,  Tomoko Matsudai ,  Yuichi Oshino

IPC分类号： H01L29/739 ,  H01L29/73

CPC分类号： H01L29/36 ,  H01L29/0692 ,  H01L29/407 ,  H01L29/7397 ,  H01L29/861

摘要： According to one embodiment, a semiconductor device includes a first electrode, a first conductivity type cathode layer, a first conductivity type base layer, a second conductivity type anode layer, a second conductivity type semiconductor layer, a first conductivity type semiconductor layer, an buried body, and a second electrode. The first conductivity type semiconductor layer is contiguous to the second conductivity type semiconductor layer in a first direction, and extends on a surface of the anode layer in a second direction that intersects perpendicularly to the first direction. The buried body includes a bottom portion and a sidewall portion. The bottom portion is in contact with the base layer. The sidewall portion is in contact with the base layer, the anode layer, the second conductivity type semiconductor layer and the first conductivity type semiconductor layer. The buried body extends in the first direction.

摘要翻译： 根据一个实施例，半导体器件包括第一电极，第一导电型阴极层，第一导电型基极层，第二导电型阳极层，第二导电类型半导体层，第一导电类型半导体层，埋入 主体和第二电极。 第一导电类型半导体层在第一方向上与第二导电类型半导体层邻接，并且在与第一方向垂直的第二方向上在阳极层的表面上延伸。 埋藏体包括底部和侧壁部分。 底部与基层接触。 侧壁部与基底层，阳极层，第二导电型半导体层和第一导电型半导体层接触。 埋藏体沿第一方向延伸。

公开(公告)号：US5315134A

公开(公告)日：1994-05-24

申请号：US896422

申请日：1992-06-10

申请人： Tsuneo Ogura ,  Kiminori Watanabe ,  Akio Nakagawa ,  Yoshihiro Yamaguchi ,  Norio Yasuhara ,  Tomoko Matsudai

发明人： Tsuneo Ogura ,  Kiminori Watanabe ,  Akio Nakagawa ,  Yoshihiro Yamaguchi ,  Norio Yasuhara ,  Tomoko Matsudai

IPC分类号： H01L29/745 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L29/7455

摘要： A thyristor with an insulated gate includes a p-type emitter layer, an n-type base layer, a p-type base layer, and an n-type emitter layer. A drain electrode contacting the p-type base layer is formed adjacent to one side of the n-type emitter layer. An n-type drain layer, which is short-circuited with the p-type base layer by the drain electrode, is formed. An n-type source layer is formed a predetermined distance away from the n-type drain layer. A turn-off insulated gate is formed between the n-type source layer and the n-type drain layer. A source electrode is connected to a cathode electrode. Thereby, turn-off capability of the thyristor can be improved.

摘要翻译： 具有绝缘栅的晶闸管包括p型发射极层，n型基极层，p型基极层和n型发射极层。 与p型基极层接触的漏电极与n型发射极层的一侧相邻地形成。 形成了由漏电极与p型基极层短路的n型漏极层。 n型源极层与n型漏极层形成规定的距离。 在n型源极层和n型漏极层之间形成有截止绝缘栅极。 源电极连接到阴极电极。 由此，能够提高晶闸管的关断能力。

公开(公告)号：US5463231A

公开(公告)日：1995-10-31

申请号：US353385

申请日：1994-12-02

申请人： Tsuneo Ogura ,  Kiminori Watanabe ,  Akio Nakagawa ,  Yoshihiro Yamaguchi ,  Norio Yasuhara ,  Tomoko Matsudai ,  Shigeru Hasegawa ,  Kazuya Nakayama

发明人： Tsuneo Ogura ,  Kiminori Watanabe ,  Akio Nakagawa ,  Yoshihiro Yamaguchi ,  Norio Yasuhara ,  Tomoko Matsudai ,  Shigeru Hasegawa ,  Kazuya Nakayama

IPC分类号： H01L27/06 ,  H01L29/74 ,  H01L29/745 ,  H01L29/749 ,  H01L31/111

CPC分类号： H01L27/0617 ,  H01L29/7436 ,  H01L29/7455 ,  H01L29/749

摘要： A thyristor with insulated gates includes turn-off and turn-on MOSFETs. The turn-on MOSFET has a turn-on gate employing a p-type base as a channel and extending over an n-type base and an n-type emitter. The turn-off MOSFET has n-type drain and source layers formed in a p-type base layer, and a turn-off gate extending over the drain and source layers. The n-type drain layer is short-circuited with the p-type base layer via a drain electrode. The drain electrode is formed near an n-type emitter layer. When the thyristor is to be turned off, the first voltage is applied to the turn-on gate, and the second voltage is applied to the turn-off gate while the first voltage is applied to the turn-on gate. After the application of the second voltage continues for a predetermined period of time, the application of the first voltage to the turn-on gate is stopped. With this operation, the thyristor can be turned off even with a large current.

公开(公告)号：US20130240947A1

公开(公告)日：2013-09-19

申请号：US13680849

申请日：2012-11-19

申请人： Tomoko Matsudai ,  Tsuneo Ogura

发明人： Tomoko Matsudai ,  Tsuneo Ogura

IPC分类号： H01L29/739 ,  H01L29/66

CPC分类号： H01L29/7397 ,  H01L27/0623 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/0834 ,  H01L29/1004 ,  H01L29/407 ,  H01L29/417 ,  H01L29/41708 ,  H01L29/45 ,  H01L29/6609 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/8613

摘要： A semiconductor device formed on a substrate of a first conductivity type, including a base layer of a second conductivity disposed on a first face of the substrate, an anode layer with a higher dopant amount in a portion of the base layer, an IGBT region formed on the base layer, a diode region formed on the anode layer, a trench extending from the top of the IGBT and diode regions in to the substrate. The area occupied by the diode region is different from the area occupied by the IGBT region, but they share collector and emitter electrodes. The contact area between the diode anode layer and the emitter electrode may be adjusted by the arrangement of trenches.

摘要翻译： 一种半导体器件，形成在第一导电类型的衬底上，包括设置在衬底的第一面上的第二导电性的基底层，在基底层的一部分中具有较高掺杂量的阳极层，形成的IGBT区域 在基极层上，形成在阳极层上的二极管区域，从IGBT顶部延伸的沟槽和二极管区域延伸到衬底。 二极管区域所占的面积与IGBT区域所占的面积不同，但共享集电极和发射极。 二极管阳极层和发射电极之间的接触面积可以通过沟槽的布置进行调节。

公开(公告)号：US5428228A

公开(公告)日：1995-06-27

申请号：US164756

申请日：1993-12-10

申请人： Tsuneo Ogura ,  Kiminori Watanabe ,  Akio Nakagawa ,  Yoshihiro Yamaguchi ,  Norio Yasuhara ,  Tomoko Matsudai ,  Shigeru Hasegawa ,  Kazuya Nakayama

发明人： Tsuneo Ogura ,  Kiminori Watanabe ,  Akio Nakagawa ,  Yoshihiro Yamaguchi ,  Norio Yasuhara ,  Tomoko Matsudai ,  Shigeru Hasegawa ,  Kazuya Nakayama

IPC分类号： H01L27/06 ,  H01L29/74 ,  H01L29/745 ,  H01L29/749 ,  H01L29/747

CPC分类号： H01L27/0617 ,  H01L29/7436 ,  H01L29/7455 ,  H01L29/749

摘要： A thyristor with insulated gates includes turn-off and turn-on MOSFETs. The turn-on MOSFET has a turn-on gate employing a p-type base as a channel and extending over an n-type base and an n-type emitter. The turn-off MOSFET has n-type drain and source layers formed in a p-type base layer, and a turn-off gate extending over the drain and source layers. The n-type drain layer is short-circuited with the p-type base layer via a drain electrode. The drain electrode is formed near an n-type emitter layer. When the thyristor is to be turned off, the first voltage is applied to the turn-on gate, and the second voltage is applied to the turn-off gate while the first voltage is applied to the turn-on gate. After the application of the second voltage continues for a predetermined period of time, the application of the first voltage to the turn-on gate is stopped. With this operation, the thyristor can be turned off even with a large current.

摘要翻译： 具有绝缘栅极的晶闸管包括关断和导通MOSFET。 导通MOSFET具有采用p型基极作为沟道并在n型基极和n型发射极上延伸的导通栅极。 关断MOSFET具有形成在p型基极层中的n型漏极和源极层，以及在漏极和源极层上延伸的截止栅极。 n型漏极层经由漏电极与p型基极层短路。 在n型发射极层附近形成漏电极。 当晶闸管关断时，第一电压被施加到导通栅极，并且第二电压被施加到关断栅极，同时第一电压被施加到导通栅极。 在第二电压的施加持续预定时间段之后，停止向导通门施加第一电压。 通过这种操作，即使使用大电流，晶闸管也可以关闭。

公开(公告)号：US20100096696A1

公开(公告)日：2010-04-22

申请号：US12645072

申请日：2009-12-22

申请人： Yusuke Kawaguchi ,  Norio Yasuhara ,  Tomoko Matsudai ,  Kenichi Matsushita

发明人： Yusuke Kawaguchi ,  Norio Yasuhara ,  Tomoko Matsudai ,  Kenichi Matsushita

IPC分类号： H01L29/78

CPC分类号： H01L29/0847 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： A body layer of a first conductivity type is formed on a semiconductor substrate, and a source layer of a second conductivity type is formed in a surface region of the body layer. An offset layer of the second conductivity type is formed on the semiconductor substrate, and a drain layer of the second conductivity type is formed in a surface region of the offset layer. An insulating film is embedded in a trench formed in the surface region of the offset layer between the source layer and the drain layer. A gate insulating film is formed on the body layer and the offset layer between the source layer and the insulating film. A gate electrode is formed on the gate insulating film. A first peak of an impurity concentration profile in the offset layer is formed at a position deeper than the insulating film.

摘要翻译： 在半导体衬底上形成第一导电类型的主体层，并且在主体层的表面区域中形成第二导电类型的源极层。 第二导电类型的偏移层形成在半导体衬底上，并且第二导电类型的漏极层形成在偏移层的表面区域中。 绝缘膜嵌入形成在源极层和漏极层之间的偏移层的表面区域中的沟槽中。 在主体层和源极层与绝缘膜之间的偏移层上形成栅极绝缘膜。 在栅极绝缘膜上形成栅电极。 偏移层中的杂质浓度分布的第一峰形成在比绝缘膜更深的位置。

公开(公告)号：US07692242B2

公开(公告)日：2010-04-06

申请号：US11505337

申请日：2006-08-17

申请人： Tomoko Matsudai ,  Norio Yasuhara ,  Yusuke Kawaguchi ,  Kenichi Matsushita

发明人： Tomoko Matsudai ,  Norio Yasuhara ,  Yusuke Kawaguchi ,  Kenichi Matsushita

IPC分类号： H01L29/04 ,  H01L29/06

CPC分类号： H01L29/1045 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7838

摘要： A low resistance layer is formed on a semiconductor substrate, and a high resistance layer formed on the low resistance layer. A source region of a first conductivity type is formed on a surface region of the high resistance layer. A drain region of the first conductivity type is formed at a distance from the source region. A first resurf region of the first conductivity type is formed in a surface region of the high resistance layer between the source region and the drain region. A channel region of a second conductivity type is formed between the source region and the first resurf region. A gate insulating film is formed on the channel region, and a gate electrode formed on the gate insulating film. An impurity concentration in the channel region under the gate electrode gradually lowers from the source region toward the first resurf region.

摘要翻译： 在半导体衬底上形成低电阻层，形成在低电阻层上的高电阻层。 第一导电类型的源区形成在高电阻层的表面区域上。 第一导电类型的漏极区域形成在与源极区域一定距离处。 在源极区域和漏极区域之间的高电阻层的表面区域中形成第一导电类型的第一再结晶区域。 在源极区域和第一再结晶区域之间形成第二导电类型的沟道区域。 栅极绝缘膜形成在沟道区上，栅极形成在栅极绝缘膜上。 栅电极下方的沟道区域中的杂质浓度从源极区域朝向第一再结晶区域逐渐降低。

公开(公告)号：US20100006936A1

公开(公告)日：2010-01-14

申请号：US12476147

申请日：2009-06-01

申请人： Tomoko Matsudai ,  Norio Yasuhara ,  Kazutoshi Nakamura

发明人： Tomoko Matsudai ,  Norio Yasuhara ,  Kazutoshi Nakamura

IPC分类号： H01L29/78

CPC分类号： H01L29/7835 ,  H01L21/266 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/66659

摘要： A semiconductor device includes a semiconductor layer of a first conductivity type; a deep well of a second conductivity type formed in a portion of an upper layer portion of the semiconductor layer; a well of the first conductivity type formed in a portion of an upper layer portion of the deep well; a source layer of the second conductivity type formed in the well; a drain layer of the second conductivity type formed in the well apart from the source layer; and a contact layer of the second conductivity type formed outside the well in an upper layer portion of the deep well and connected to the drain layer. The drain layer is electrically connected to the deep well via the well by applying a driving voltage between the source layer and the drain layer.

摘要翻译： 半导体器件包括第一导电类型的半导体层; 形成在半导体层的上层部分的一部分中的第二导电类型的深阱; 形成在深井的上层部分的一部分中的第一导电类型的阱; 在井中形成的第二导电类型的源极层; 第二导电类型的漏极层形成在远离源极的阱中; 以及在阱的上层部分中形成在阱外部并连接到漏极层的第二导电类型的接触层。 通过在源极层和漏极层之间施加驱动电压，漏极层通过阱与深阱电连接。

公开(公告)号：US07589389B2

公开(公告)日：2009-09-15

申请号：US12264580

申请日：2008-11-04

申请人： Tomoko Matsudai ,  Norio Yasuhara

发明人： Tomoko Matsudai ,  Norio Yasuhara

IPC分类号： H01L23/58

CPC分类号： H01L29/7816 ,  H01L29/063 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprising: a base layer of a first conductivity type selectively formed above a semiconductor substrate; a gate electrode formed on the base layer via the insulating film; a source layer of a second conductivity type selectively formed at a surface of the base layer at one side of the gate electrode; an channel implantation layer selectively formed at the surface of the base layer so as to be adjacent to the source layer below the gate electrode, the channel implantation layer having a higher concentration than the base layer; a RESURF layer of the second conductivity type selectively formed at the surface of the base layer at the other side of the gate electrode; and a drain layer of a second conductivity type being adjacent to the RESURF layer, a portion of the drain layer overlapping the base layer, and the drain layer having a higher concentration than the RESURF layer.

公开(公告)号：US07473978B2

公开(公告)日：2009-01-06

申请号：US11502387

申请日：2006-08-11

申请人： Tomoko Matsudai ,  Norio Yasuhara

发明人： Tomoko Matsudai ,  Norio Yasuhara

IPC分类号： H01L23/58

CPC分类号： H01L29/7816 ,  H01L29/063 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprising: a base layer of a first conductivity type selectively formed above a semiconductor substrate; a gate electrode formed on the base layer via the insulating film; a source layer of a second conductivity type selectively formed at a surface of the base layer at one side of the gate electrode; an channel implantation layer selectively formed at the surface of the base layer so as to be adjacent to the source layer below the gate electrode, the channel implantation layer having a higher concentration than the base layer; a RESURF layer of the second conductivity type selectively formed at the surface of the base layer at the other side of the gate electrode; and a drain layer of a second conductivity type being adjacent to the RESURF layer, a portion of the drain layer overlapping the base layer, and the drain layer having a higher concentration than the RESURF layer.

摘要翻译： 一种半导体器件，包括：选择性地形成在半导体衬底之上的第一导电类型的基极层; 经由所述绝缘膜形成在所述基底层上的栅电极; 选择性地形成在所述基极层的所述栅电极的一侧的表面处的第二导电类型的源极层; 沟道注入层，其选择性地形成在所述基底层的表面处以与所述栅极电极下方的源极层相邻，所述沟道注入层具有比所述基底层更高的浓度; 所述第二导电类型的RESURF层选择性地形成在所述基极层的所述栅极电极的另一侧的表面处; 以及与RESURF层相邻的第二导电类型的漏极层，所述漏极层的一部分与所述基极层重叠，并且所述漏极层具有比所述RESURF层更高的浓度。