公开(公告)号：US07037857B2

公开(公告)日：2006-05-02

申请号：US10737115

申请日：2003-12-16

申请人： Toni D. Van Gompel ,  Mark D. Hall ,  Mohamad Jahanbani ,  Michael D. Turner

发明人： Toni D. Van Gompel ,  Mark D. Hall ,  Mohamad Jahanbani ,  Michael D. Turner

IPC分类号： H01L21/3205 ,  H01L21/31

CPC分类号： H01L21/76283

摘要： A method for forming trench isolation in an SOI substrate begins with a pad oxide followed by an antireflective coating (ARC) over the upper semiconductor layer of the SOI substrate. The pad oxide is kept to a thickness not greater than about 100 Angstroms. An opening is formed for the trench isolation that extends into the oxide below the upper semiconductor layer to expose a surface thereof. The pad oxide is recessed along its sidewall with an isotropic etch. This is followed by a thin, not greater than 50 Angstroms, oxide grown along the sidewall of the opening. This grown oxide avoids forming a recess between the ARC and the pad oxide and also avoids forming a void between the surface of the lower oxide layer and the grown oxide. This results in avoiding polysilicon stringers when the subsequent polysilicon gate layer is formed.

摘要翻译： 在SOI衬底中形成沟槽隔离的方法开始于衬底氧化物，然后在SOI衬底的上半导体层上方具有抗反射涂层（ARC）。 衬垫氧化物保持不大于约100埃的厚度。 形成用于沟槽隔离的开口，其延伸到上半导体层下方的氧化物中以暴露其表面。 衬垫氧化物沿其侧壁凹陷，具有各向同性蚀刻。 其后是沿着开口的侧壁生长的薄的，不大于50埃的氧化物。 这种生长的氧化物避免在ARC和衬垫氧化物之间形成凹陷，并且还避免在低氧化物层的表面和生长的氧化物之间形成空隙。 这导致当形成随后的多晶硅栅极层时避免多晶硅桁条。

公开(公告)号：US20080261361A1

公开(公告)日：2008-10-23

申请号：US11788184

申请日：2007-04-18

申请人： Konstantin V. Loiko ,  Toni D. Van Gompel ,  Rode R. Mora ,  Michael D. Turner ,  Brian A. Winstead ,  Mark D. Hall

发明人： Konstantin V. Loiko ,  Toni D. Van Gompel ,  Rode R. Mora ,  Michael D. Turner ,  Brian A. Winstead ,  Mark D. Hall

IPC分类号： H01L21/8238 ,  H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66477 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7846

摘要： A method for making a semiconductor device is provided which comprises (a) providing a layer stack comprising a semiconductor layer (211) and a dielectric layer (209) disposed between the substrate and the semiconductor layer, (b) creating a trench (210) which extends through the semiconductor layer and which exposes a portion of the dielectric layer, the trench having a sidewall, (c) creating a spacer structure (221) which comprises a first material and which is adjacent to the sidewall of the trench, and (d) forming a stressor layer (223) which comprises a second material and which is disposed on the bottom of the trench.

摘要翻译： 提供一种制造半导体器件的方法，其包括（a）提供包括半导体层（211）和布置在所述衬底和所述半导体层之间的介电层（209）的层堆叠，（b）产生沟槽（210） 其延伸穿过所述半导体层并且暴露所述电介质层的一部分，所述沟槽具有侧壁，（c）产生包括第一材料并且邻近所述沟槽的侧壁的间隔结构（221）和（ d）形成包含第二材料并且设置在沟槽底部的应力层（223）。

公开(公告)号：US08236638B2

公开(公告)日：2012-08-07

申请号：US11788184

申请日：2007-04-18

申请人： Konstantin V. Loiko ,  Toni D. Van Gompel ,  Rode R. Mora ,  Michael D. Turner ,  Brian A. Winstead ,  Mark D. Hall

发明人： Konstantin V. Loiko ,  Toni D. Van Gompel ,  Rode R. Mora ,  Michael D. Turner ,  Brian A. Winstead ,  Mark D. Hall

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/76

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66477 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7846

摘要： A method for making a semiconductor device is provided which includes (a) providing a layer stack comprising a semiconductor layer (211) and a dielectric layer (209) disposed between the substrate and the semiconductor layer, (b) creating a trench (210) which extends through the semiconductor layer and which exposes a portion of the dielectric layer, the trench having a sidewall, (c) creating a spacer structure (221) which comprises a first material and which is adjacent to the sidewall of the trench, and (d) forming a stressor layer (223) which comprises a second material and which is disposed on the bottom of the trench.

摘要翻译： 提供一种制造半导体器件的方法，其包括（a）提供包括半导体层（211）和设置在所述衬底和所述半导体层之间的电介质层（209）的层堆叠，（b）产生沟槽（210） 其延伸穿过所述半导体层并且暴露所述电介质层的一部分，所述沟槽具有侧壁，（c）产生包括第一材料并且邻近所述沟槽的侧壁的间隔结构（221）和（ d）形成包含第二材料并且设置在沟槽底部的应力层（223）。

公开(公告)号：US08766362B2

公开(公告)日：2014-07-01

申请号：US13548304

申请日：2012-07-13

申请人： Konstantin V. Loiko ,  Toni D. Van Gompel ,  Rode R. Mora ,  Michael D. Turner ,  Brian A. Winstead ,  Mark D. Hall

发明人： Konstantin V. Loiko ,  Toni D. Van Gompel ,  Rode R. Mora ,  Michael D. Turner ,  Brian A. Winstead ,  Mark D. Hall

IPC分类号： H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66477 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7846

摘要： A method for making a semiconductor device is provided which includes (a) providing a layer stack comprising a semiconductor layer (211) and a dielectric layer (209) disposed between the substrate and the semiconductor layer, (b) creating a trench (210) which extends through the semiconductor layer and which exposes a portion of the dielectric layer, the trench having a sidewall, (c) creating a spacer structure (221) which comprises a first material and which is adjacent to the sidewall of the trench, and (d) forming a stressor layer (223) which comprises a second material and which is disposed on the bottom of the trench.

摘要翻译： 提供一种制造半导体器件的方法，其包括（a）提供包括半导体层（211）和设置在所述衬底和所述半导体层之间的电介质层（209）的层堆叠，（b）产生沟槽（210） 其延伸穿过所述半导体层并且暴露所述电介质层的一部分，所述沟槽具有侧壁，（c）产生包括第一材料并且邻近所述沟槽的侧壁的间隔结构（221）和（ d）形成包含第二材料并且设置在沟槽底部的应力层（223）。

公开(公告)号：US07491622B2

公开(公告)日：2009-02-17

申请号：US11409790

申请日：2006-04-24

申请人： Michael D. Turner ,  Mohamad M. Jahanbani ,  Toni D. Van Gompel ,  Mark D. Hall

发明人： Michael D. Turner ,  Mohamad M. Jahanbani ,  Toni D. Van Gompel ,  Mark D. Hall

IPC分类号： H01L21/76 ,  H01L23/58

CPC分类号： H01L21/02274 ,  H01L21/02211 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/3185 ,  H01L21/76283 ,  H01L21/823481 ,  H01L21/84

摘要： A process of forming an electronic device can include patterning a semiconductor layer to define an opening extending to an insulating layer, wherein the insulating layer lies between a substrate and the semiconductor layer. After patterning a semiconductor layer, the semiconductor layer can have a sidewall and a surface, the surface can be spaced apart from the insulating layer, and the sidewall can extend from the surface towards the insulating layer. The process can also include chemical vapor depositing a first layer adjacent to the sidewall, wherein the first layer lies within the opening and adjacent to the sidewall, and is spaced apart from the surface. Chemical vapor depositing the first layer can be performed using an inductively coupled plasma.

摘要翻译： 形成电子器件的过程可以包括图案化半导体层以限定延伸到绝缘层的开口，其中绝缘层位于衬底和半导体层之间。 在图案化半导体层之后，半导体层可以具有侧壁和表面，表面可以与绝缘层间隔开，并且侧壁可以从表面延伸到绝缘层。 该方法还可以包括化学气相沉积邻近侧壁的第一层，其中第一层位于开口内且与侧壁相邻并且与表面间隔开。 可以使用电感耦合等离子体进行沉积第一层的化学气相沉积。

公开(公告)号：US20140299935A1

公开(公告)日：2014-10-09

申请号：US14308816

申请日：2014-06-19

申请人： Konstantin V. Loiko ,  Toni D. Van Gompel ,  Rode R. Mora ,  Michael D. Turner ,  Brian A. Winstead ,  Mark D. Hall

发明人： Konstantin V. Loiko ,  Toni D. Van Gompel ,  Rode R. Mora ,  Michael D. Turner ,  Brian A. Winstead ,  Mark D. Hall

IPC分类号： H01L27/12 ,  H01L29/78 ,  H01L29/161 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66477 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7846

摘要： A method for making a semiconductor device is provided which includes (a) providing a layer stack comprising a semiconductor layer (211) and a dielectric layer (209) disposed between the substrate and the semiconductor layer, (b) creating a trench (210) which extends through the semiconductor layer and which exposes a portion of the dielectric layer, the trench having a sidewall, (c) creating a spacer structure (221) which comprises a first material and which is adjacent to the sidewall of the trench, and (d) forming a stressor layer (223) which comprises a second material and which is disposed on the bottom of the trench.

摘要翻译： 提供一种制造半导体器件的方法，其包括（a）提供包括半导体层（211）和设置在所述衬底和所述半导体层之间的电介质层（209）的层堆叠，（b）产生沟槽（210） 其延伸穿过所述半导体层并且暴露所述电介质层的一部分，所述沟槽具有侧壁，（c）产生包括第一材料并且邻近所述沟槽的侧壁的间隔结构（221）和（ d）形成包含第二材料并且设置在沟槽底部的应力层（223）。

公开(公告)号：USD954601S1

公开(公告)日：2022-06-14

申请号：US29764839

申请日：2021-01-04

申请人： Nicholas A. Malachowski ,  Eugenio Sellaro-Neto ,  Alexander Tannen ,  Chris Piscitelli ,  Mark D. Hall ,  Mark T. Allen

设计人： Nicholas A. Malachowski ,  Eugenio Sellaro-Neto ,  Alexander Tannen ,  Chris Piscitelli ,  Mark D. Hall ,  Mark T. Allen

公开(公告)号：US20170366025A1

公开(公告)日：2017-12-21

申请号：US15183012

申请日：2016-06-15

申请人： David R. Hall ,  Mark D. Hall ,  Clint Cook ,  Davido Hyer ,  Joe Fox ,  Jedediah Knight

发明人： David R. Hall ,  Mark D. Hall ,  Clint Cook ,  Davido Hyer ,  Joe Fox ,  Jedediah Knight

IPC分类号： H02J7/00

CPC分类号： H02J7/0044 ,  H02J7/0047

摘要： An apparatus is disclosed that includes a battery-powered wireless switch and a switch dock. The switch includes a microcontroller, a short range wireless transmitter, and one or more tactile control buttons. Additionally, the switch includes one or more docking prongs. Each docking prong is contained within a groove in a switch back, with pivot pins through one end of each docking prong perpendicular to a prong longitudinal axis and parallel to the switch back. The switch also includes flexible strips coupled to the same end of each docking prong as the pivot pins, and a prong extender button coupled to the flexible strips. The dock includes one or more docking prong slots, where the number of slots matches the number of prongs. The prongs fit in the slots to mount the switch to the dock.

公开(公告)号：US20170339004A1

公开(公告)日：2017-11-23

申请号：US15156729

申请日：2016-05-17

申请人： David R. Hall ,  Mark D. Hall ,  Craig Boswell ,  Jedediah Knight

发明人： David R. Hall ,  Mark D. Hall ,  Craig Boswell ,  Jedediah Knight

IPC分类号： H04L12/24 ,  H04L12/28 ,  H04L12/44 ,  H04L12/26

CPC分类号： H04L12/2838 ,  H04L12/44 ,  H04L41/0663 ,  H04L43/0805 ,  H04L43/50

摘要： A redundant star network and methods for communicating over the network are disclosed. The network includes a peripheral device, a first network hub, and a second network hub. Each of the peripheral device, the first network hub, and the second network hub includes a wireless long range transceiver and at least one microcontroller. The first and second network hub microcontrollers store system operation information that includes instructions for operating the peripheral device and instructions for designating a peripheral device control hub. Additionally, the first and second network hub microcontrollers each include firmware for testing whether the other hub is operational and updating the system operation information to change the peripheral device control hub if it is non-operational. In some embodiments, the network is connected to a cloud server that communicates system updates to a user device.

公开(公告)号：US09362280B2

公开(公告)日：2016-06-07

申请号：US13893026

申请日：2013-05-13

申请人： Gauri V. Karve ,  Mark D. Hall ,  Srikanth B. Samavedam

发明人： Gauri V. Karve ,  Mark D. Hall ,  Srikanth B. Samavedam

IPC分类号： H01L21/70 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/10

CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/1054

摘要： An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon.