利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

20 条记录 (耗时 0.029 秒)

    SIDEWALL IMAGE TRANSFER PROCESSES FOR FORMING MULTIPLE LINE-WIDTHS
    8.
    发明申请
    SIDEWALL IMAGE TRANSFER PROCESSES FOR FORMING MULTIPLE LINE-WIDTHS 失效
    用于形成多个线宽的平面图像传输过程

    公开(公告)号：US20080206996A1

    公开(公告)日：2008-08-28

    申请号：US11680204

    申请日：2007-02-28

    申请人： Toshiharu Furukawa ,  John G. Gaudiello ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger

    发明人： Toshiharu Furukawa ,  John G. Gaudiello ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger

    IPC分类号： H01L21/302

    CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28123

    摘要： A method for simultaneously forming multiple line-widths, one of which is less than that achievable employing conventional lithographic techniques. The method includes providing a structure which includes a memory layer and a sidewall image transfer (SIT) layer on top of the memory layer. Then, the SIT layer is patterned resulting in a SIT region. Then, the SIT region is used as a blocking mask during directional etching of the memory layer resulting in a first memory region. Then, a side wall of the SIT region is retreated a retreating distance D in a reference direction resulting in a SIT portion. Said patterning comprises a lithographic process. The retreating distance D is less than a critical dimension CD associated with the lithographic process. The SIT region includes a first dimension W2 and a second dimension W3 in the reference direction, wherein CD

    摘要翻译： 同时形成多个线宽的方法，其中之一小于使用常规光刻技术可实现的线宽。 该方法包括提供在存储层顶部包括存储层和侧壁图像传输（SIT）层的结构。 然后，对SIT层进行图案化，形成SIT区域。 然后，在存储层的定向蚀刻期间，将SIT区域用作阻挡掩模，产生第一存储区域。 然后，SIT区域的侧壁在参考方向上退回退避距离D，导致SIT部分。 所述图案化包括光刻工艺。 退回距离D小于与光刻工艺相关联的关键尺寸CD。 SIT区域包括参考方向上的第一维W 2和第二维W 3，其中CD

    SHALLOW TRENCH ISOLATION FILL BY LIQUID PHASE DEPOSITION OF SiO2
    9.
    发明申请
    SHALLOW TRENCH ISOLATION FILL BY LIQUID PHASE DEPOSITION OF SiO2 审中-公开
    通过SiO 2的液相沉积沉积分离膜

    公开(公告)号：US20080197448A1

    公开(公告)日：2008-08-21

    申请号：US12112549

    申请日：2008-04-30

    申请人： Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger ,  Peter H. Mitchell ,  Larry Alan Nesbit

    发明人： Mark Charles Hakey ,  Steven John Holmes ,  David Vaclav Horak ,  Charles William Koburger ,  Peter H. Mitchell ,  Larry Alan Nesbit

    IPC分类号： H01L29/00

    CPC分类号： H01L27/1203 ,  H01L21/76283 ,  H01L21/84

    摘要： To isolate two active regions formed on a silicon-on-insulator (SOI) substrate, a shallow trench isolation region is filled with liquid phase deposited silicon dioxide (LPD-SiO2) while avoiding covering the active areas with the oxide. By selectively depositing the oxide in this manner, the polishing needed to planarize the wafer is significantly reduced as compared to a chemical-vapor deposited oxide layer that covers the entire wafer surface. Additionally, the LPD-SiO2 does not include the growth seams that CVD silicon dioxide does. Accordingly, the etch rate of the LPD-SiO2 is uniform across its entire expanse thereby preventing cavities and other etching irregularities present in prior art shallow trench isolation regions in which the etch rate of growth seams exceeds that of the other oxide areas.

    摘要翻译： 为了隔离形成在绝缘体上硅（SOI）衬底上的两个有源区，浅沟槽隔离区填充有液相沉积二氧化硅（LPD-SiO 2），同时避免覆盖有源区 与氧化物。 通过以这种方式选择性地沉积氧化物，与覆盖整个晶片表面的化学气相沉积氧化物层相比，平坦化晶片所需的抛光显着降低。 此外，LPD-SiO 2不包括CVD二氧化硅的生长接缝。 因此，LPD-SiO 2的蚀刻速率在其整个宽度上是均匀的，从而防止存在于现有技术的浅沟槽隔离区域中的空穴和其它蚀刻不规则性，其中生长接缝的蚀刻速率超过 其他氧化物区域。

    WRAP-AROUND GATE FIELD EFFECT TRANSISTOR
    10.
    发明申请
    WRAP-AROUND GATE FIELD EFFECT TRANSISTOR 失效
    封边栅场效应晶体管

    公开(公告)号：US20080206937A1

    公开(公告)日：2008-08-28

    申请号：US12114180

    申请日：2008-05-02

    申请人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger ,  Peter H. Mitchell

    发明人： Toshiharu Furukawa ,  Mark Charles Hakey ,  David Vaclav Horak ,  Charles William Koburger ,  Peter H. Mitchell

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66772 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/78645 ,  H01L29/78648

    摘要： A field effect transistor is formed having wrap-around, vertically-aligned, dual gate electrodes. Starting with a silicon-on-insulator (SOI) structure having a buried silicon island, a vertical reference edge is defined, by creating a cavity within the SOI structure, and used during two etch-back steps that can be reliably performed. The first etch-back removes a portion of an oxide layer for a first distance over which a gate conductor material is then applied. The second etch-back removes a portion of the gate conductor material for a second distance. The difference between the first and second distances defines the gate length of the eventual device. After stripping away the oxide layers, a vertical gate electrode is revealed that surrounds the buried silicon island on all four side surfaces.

    摘要翻译： 形成具有环绕，垂直排列的双栅电极的场效应晶体管。 从具有掩埋硅岛的绝缘体上硅（SOI）结构开始，通过在SOI结构内产生空腔并在可以可靠地执行的两个回蚀步骤期间使用垂直参考边缘。 第一次回蚀将氧化物层的一部分去除第一距离，然后施加栅极导体材料。 第二次回蚀将栅极导体材料的一部分移除第二距离。 第一和第二距离之间的差异定义了最终设备的栅极长度。 剥离氧化物层后，显示出在所有四个侧表面上包围掩埋硅岛的垂直栅电极。