公开(公告)号：US20130075732A1

公开(公告)日：2013-03-28

申请号：US13604962

申请日：2012-09-06

申请人： Toshihiko SAITO ,  Atsuo ISOBE ,  Kazuya HANAOKA ,  Junichi KOEZUKA ,  Shinya SASAGAWA ,  Motomu KURATA ,  Akihiro ISHIZUKA

发明人： Toshihiko SAITO ,  Atsuo ISOBE ,  Kazuya HANAOKA ,  Junichi KOEZUKA ,  Shinya SASAGAWA ,  Motomu KURATA ,  Akihiro ISHIZUKA

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/7869 ,  H01L27/1225

摘要： A miniaturized transistor having high electric characteristics is provided with high yield. In a semiconductor device including the transistor, high performance, high reliability, and high productivity are achieved. In a semiconductor device including a transistor in which an oxide semiconductor film, a gate insulating film, and a gate electrode layer on side surfaces of which sidewall insulating layers are provided are stacked in this order, source and drain electrode layers are provided in contact with the oxide semiconductor film and the sidewall insulating layers. In a process for manufacturing the semiconductor device, a conductive film and an interlayer insulating film are stacked to cover the oxide semiconductor film, the sidewall insulating layers, and the gate electrode layer, and the interlayer insulating film and the conductive film over the gate electrode layer are removed by a chemical mechanical polishing method, so that the source and drain electrode layers are formed.

摘要翻译： 提供具有高电特性的小型化晶体管，其产率高。 在包括晶体管的半导体器件中，实现了高性能，高可靠性和高生产率。 在包括晶体管的半导体器件中，依次堆叠其中设置有侧壁绝缘层的侧表面上的氧化物半导体膜，栅极绝缘膜和栅极电极层的晶体管，源极和漏极电极层被设置为与 氧化物半导体膜和侧壁绝缘层。 在制造半导体器件的过程中，层叠导电膜和层间绝缘膜以覆盖氧化物半导体膜，侧壁绝缘层和栅极电极层，以及栅极上的层间绝缘膜和导电膜 通过化学机械抛光方法去除层，从而形成源极和漏极电极层。

公开(公告)号：US20110147745A1

公开(公告)日：2011-06-23

申请号：US12973123

申请日：2010-12-20

申请人： Shinya SASAGAWA ,  Akihiro ISHIZUKA ,  Shinobu FURUKAWA ,  Motomu KURATA

发明人： Shinya SASAGAWA ,  Akihiro ISHIZUKA ,  Shinobu FURUKAWA ,  Motomu KURATA

IPC分类号： H01L29/12 ,  H01L21/20

CPC分类号： H01L29/66765 ,  H01L29/78669 ,  H01L29/78678 ,  H01L29/78696

摘要： An embodiment is a thin film transistor which includes a gate electrode layer, a gate insulating layer provided so as to cover the gate electrode layer; a first semiconductor layer entirely overlapped with the gate electrode layer; a second semiconductor layer provided over and in contact with the first semiconductor layer and having a lower carrier mobility than the first semiconductor layer; an impurity semiconductor layer provided in contact with the second semiconductor layer; a sidewall insulating layer provided so as to cover at least a sidewall of the first semiconductor layer; and a source and drain electrode layers provided in contact with at least the impurity semiconductor layer. The second semiconductor layer may consist of parts which are apart from each other over the first semiconductor layer.

摘要翻译： 一个实施例是一种薄膜晶体管，其包括栅极电极层，设置为覆盖栅极电极层的栅极绝缘层; 与栅电极层完全重叠的第一半导体层; 第二半导体层，设置在第一半导体层上并与第一半导体层接触，并具有比第一半导体层低的载流子迁移率; 设置成与所述第二半导体层接触的杂质半导体层; 侧壁绝缘层，设置成覆盖所述第一半导体层的至少一个侧壁; 以及与至少所述杂质半导体层接触地设置的源极和漏极电极层。 第二半导体层可以由在第一半导体层上彼此分开的部分组成。

公开(公告)号：US20100047997A1

公开(公告)日：2010-02-25

申请号：US12505020

申请日：2009-07-17

申请人： Akihiro ISHIZUKA ,  Shinya SASAGAWA ,  Motomu KURATA ,  Atsushi HIKOSAKA ,  Taiga MURAOKA ,  Hitoshi NAKAYAMA

发明人： Akihiro ISHIZUKA ,  Shinya SASAGAWA ,  Motomu KURATA ,  Atsushi HIKOSAKA ,  Taiga MURAOKA ,  Hitoshi NAKAYAMA

IPC分类号： H01L21/762

CPC分类号： H01L21/76254

摘要： It is an object of the preset invention to increase adhesiveness of a semiconductor layer and a base substrate and to reduce defective bonding. An oxide film is formed on a semiconductor substrate and the semiconductor substrate is irradiated with accelerated ions through the oxide film, whereby an embrittled region is formed at a predetermined depth from a surface of the semiconductor substrate. Plasma treatment is performed on the oxide film on the semiconductor substrate and the base substrate by applying a bias voltage, the surface of the semiconductor substrate and a surface of the base substrate are disposed opposite to each other, a surface of the oxide film is bonded to the surface of the base substrate, heat treatment is performed after the surface of the oxide film is bonded to the surface of the base substrate, and separation is caused along the embrittled region, whereby a semiconductor layer is formed over the base substrate with the oxide film interposed therebetween.

摘要翻译： 本发明的一个目的是增加半导体层和基底衬底的粘附性并减少不良接合。 在半导体衬底上形成氧化物膜，半导体衬底通过氧化膜照射加速离子，从而在半导体衬底的表面形成预定深度的脆化区域。 通过施加偏置电压对半导体衬底和基底衬底上的氧化物膜进行等离子体处理，半导体衬底的表面和基底衬底的表面彼此相对设置，氧化膜的表面被接合 在基底表面上进行热处理之后，在氧化膜的表面接合到基底表面之后进行热处理，沿脆化区域分离，由此在基底基板上形成半导体层 氧化膜。

公开(公告)号：US20110287605A1

公开(公告)日：2011-11-24

申请号：US13198171

申请日：2011-08-04

申请人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Akihisa SHIMOMURA ,  Junpei MOMO ,  Motomu KURATA ,  Taiga MURAOKA ,  Kosei NEI

发明人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Akihisa SHIMOMURA ,  Junpei MOMO ,  Motomu KURATA ,  Taiga MURAOKA ,  Kosei NEI

IPC分类号： H01L21/762

CPC分类号： H01L21/76254

摘要： Forming an insulating film on a surface of the single crystal semiconductor substrate, forming a fragile region in the single crystal semiconductor substrate by irradiating the single crystal semiconductor substrate with an ion beam through the insulating film, forming a bonding layer over the insulating film, bonding a supporting substrate to the single crystal semiconductor substrate by interposing the bonding layer between the supporting substrate and the single crystal semiconductor substrate, dividing the single crystal semiconductor substrate at the fragile region to separate the single crystal semiconductor substrate into a single crystal semiconductor layer attached to the supporting substrate, performing first dry etching treatment on a part of the fragile region remaining on the single crystal semiconductor layer, performing second dry etching treatment on a surface of the single crystal semiconductor layer subjected to the first etching treatment, and irradiating the single crystal semiconductor layer with laser light.

摘要翻译： 在单晶半导体基板的表面上形成绝缘膜，在单晶半导体基板中通过用离子束照射单晶半导体基板通过绝缘膜形成脆性区域，在绝缘膜上形成接合层， 通过将支撑基板和单晶半导体基板之间的接合层插入到单晶半导体基板的支撑基板上，将单晶半导体基板分割为脆性区域，将单晶半导体基板分离成单晶半导体层， 所述支撑基板对残留在所述单晶半导体层上的所述脆性区域的一部分进行第一干蚀刻处理，对经过所述第一蚀刻处理的所述单晶半导体层的表面进行第二干蚀刻处理， 具有激光的晶体半导体层。

公开(公告)号：US20110193080A1

公开(公告)日：2011-08-11

申请号：US13014081

申请日：2011-01-26

申请人： Shunpei YAMAZAKI ,  Hiromichi GODO ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Motomu KURATA ,  Mayumi MIKAMI

发明人： Shunpei YAMAZAKI ,  Hiromichi GODO ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Motomu KURATA ,  Mayumi MIKAMI

IPC分类号： H01L29/78

CPC分类号： H01L29/7869 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/66969 ,  Y10T428/24421

摘要： One object is to provide a semiconductor device that includes an oxide semiconductor and is reduced in size with favorable characteristics maintained. The semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode in contact with the oxide semiconductor layer, a gate electrode overlapping with the oxide semiconductor layer; and a gate insulating layer between the oxide semiconductor layer and the gate electrode. The source electrode or the drain electrode includes a first conductive layer and a second conductive layer having a region extended in a channel length direction from an end face of the first conductive layer. The sidewall insulating layer has a length of a bottom surface in the channel length direction smaller than a length in the channel length direction of the extended region of the second conductive layer and is provided over the extended region.

摘要翻译： 一个目的是提供一种包括氧化物半导体的半导体器件，并且尺寸减小，并保持良好的特性。 半导体器件包括与氧化物半导体层接触的氧化物半导体层，源电极和漏电极，与氧化物半导体层重叠的栅电极; 以及在氧化物半导体层和栅电极之间的栅极绝缘层。 源电极或漏极包括第一导电层和具有从第一导电层的端面在沟道长度方向上延伸的区域的第二导电层。 侧壁绝缘层的沟道长度方向的底面的长度小于第二导电层的延伸区域的沟道长度方向的长度，并且设置在延伸区域上。

公开(公告)号：US20090029514A1

公开(公告)日：2009-01-29

申请号：US12178356

申请日：2008-07-23

申请人： Tomokazu YOKOI ,  Atsuo ISOBE ,  Motomu KURATA ,  Takeshi SHICHI ,  Daisuke OHGARANE ,  Takashi SHINGU

发明人： Tomokazu YOKOI ,  Atsuo ISOBE ,  Motomu KURATA ,  Takeshi SHICHI ,  Daisuke OHGARANE ,  Takashi SHINGU

IPC分类号： H01L21/336

CPC分类号： H01L29/66765

摘要： A method for manufacturing a semiconductor device, by which a bottom gate thin film transistor that has an improved S value and a channel forming region with a smaller thickness than that of a source region and a drain region can be manufactured in a simple process. An island-like conductive film is formed over a surface of an insulating substrate in a portion corresponding to a channel forming region, and is covered with an insulating film to form a projection portion. After an amorphous semiconductor film is deposited to cover the projection portion, the amorphous semiconductor film is irradiated with laser light so as to be melted and crystallized. Part of the melted semiconductor over the projection portion flows into regions adjacent to both sides of the projection portion, which results in reduction in thickness of the semiconductor film over the projection portion (channel forming region).

摘要翻译： 一种制造半导体器件的方法，通过该方法可以以简单的方法制造具有改善的S值的底栅极薄膜晶体管和具有比源极区和漏极区更小的厚度的沟道形成区。 在对应于沟道形成区域的部分的绝缘基板的表面上形成岛状导电膜，并且被绝缘膜覆盖以形成突出部。 在沉积非晶半导体膜以覆盖突出部分之后，用激光照射非晶半导体膜以使其熔化并结晶。 突出部分上的熔融半导体的一部分流入与突出部分的两侧相邻的区域，这导致半导体膜在突出部分（沟道形成区域）上的厚度减小。

公开(公告)号：US20120193625A1

公开(公告)日：2012-08-02

申请号：US13357902

申请日：2012-01-25

申请人： Shinya SASAGAWA ,  Motomu KURATA

发明人： Shinya SASAGAWA ,  Motomu KURATA

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/66969 ,  H01L21/441 ,  H01L29/41733 ,  H01L29/7869

摘要： An object is to provide a semiconductor device in which defects are reduced and miniaturization is achieved while favorable characteristics are maintained. A semiconductor layer is formed; a first conductive layer is formed over the semiconductor layer; the first conductive layer is etched with use of a first resist mask to form a second conductive layer having a recessed portion; the first resist mask is reduced in size to form a second resist mask; the second conductive layer is etched with use of the second resist mask to form source and drain electrodes each having a projecting portion with a tapered shape at the peripheries; a gate insulating layer is formed over the source and drain electrodes to be in contact with part of the semiconductor layer; and a gate electrode is formed in a portion over the gate insulating layer and overlapping with the semiconductor layer.

摘要翻译： 本发明的目的是提供一种在保持有利特性的同时减小缺陷并实现小型化的半导体器件。 形成半导体层; 在半导体层上形成第一导电层; 使用第一抗蚀剂掩模蚀刻第一导电层以形成具有凹部的第二导电层; 第一抗蚀剂掩模的尺寸减小以形成第二抗蚀剂掩模; 使用第二抗蚀剂掩模蚀刻第二导电层，以形成在周边具有锥形形状的突出部分的源极和漏极; 在源极和漏极上形成栅极绝缘层以与半导体层的一部分接触; 并且栅极电极形成在栅极绝缘层上方并与半导体层重叠的部分。

公开(公告)号：US20090239354A1

公开(公告)日：2009-09-24

申请号：US12399047

申请日：2009-03-06

申请人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Akihisa SHIMOMURA ,  Junpei MOMO ,  Motomu KURATA ,  Taiga MURAOKA ,  Kosei NEI

发明人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Akihisa SHIMOMURA ,  Junpei MOMO ,  Motomu KURATA ,  Taiga MURAOKA ,  Kosei NEI

IPC分类号： H01L21/762

CPC分类号： H01L21/76254

摘要： Forming an insulating film on a surface of the single crystal semiconductor substrate, forming a fragile region in the single crystal semiconductor substrate by irradiating the single crystal semiconductor substrate with an ion beam through the insulating film, forming a bonding layer over the insulating film, bonding a supporting substrate to the single crystal semiconductor substrate by interposing the bonding layer between the supporting substrate and the single crystal semiconductor substrate, dividing the single crystal semiconductor substrate at the fragile region to separate the single crystal semiconductor substrate into a single crystal semiconductor layer attached to the supporting substrate, performing first dry etching treatment on a part of the fragile region remaining on the single crystal semiconductor layer, performing second dry etching treatment on a surface of the single crystal semiconductor layer subjected to the first etching treatment, and irradiating the single crystal semiconductor layer with laser light.

摘要翻译： 在单晶半导体基板的表面上形成绝缘膜，在单晶半导体基板中通过用离子束照射单晶半导体基板通过绝缘膜形成脆性区域，在绝缘膜上形成接合层， 通过将支撑基板和单晶半导体基板之间的接合层插入到单晶半导体基板的支撑基板上，将单晶半导体基板分割为脆性区域，将单晶半导体基板分离成单晶半导体层， 所述支撑基板对残留在所述单晶半导体层上的所述脆性区域的一部分进行第一干蚀刻处理，对经过所述第一蚀刻处理的所述单晶半导体层的表面进行第二干蚀刻处理， 具有激光的晶体半导体层。

公开(公告)号：US20110180796A1

公开(公告)日：2011-07-28

申请号：US13008285

申请日：2011-01-18

申请人： Shunpei YAMAZAKI ,  Hiromichi GODO ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Motomu KURATA ,  Mayumi MIKAMI

发明人： Shunpei YAMAZAKI ,  Hiromichi GODO ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Motomu KURATA ,  Mayumi MIKAMI

IPC分类号： H01L29/24

CPC分类号： H01L29/7869

摘要： An object is to provide a semiconductor device including an oxide semiconductor, which maintains favorable characteristics and achieves miniaturization. The semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode in contact with the oxide semiconductor layer, a gate electrode overlapping with the oxide semiconductor layer, and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode, in which the source electrode and the drain electrode each include a first conductive layer, and a second conductive layer having a region which extends in a channel length direction from an end portion of the first conductive layer.

摘要翻译： 本发明的目的是提供一种包含氧化物半导体的半导体器件，其保持有利的特性并实现小型化。 半导体器件包括与氧化物半导体层接触的氧化物半导体层，源极和漏电极，与氧化物半导体层重叠的栅电极，以及设置在氧化物半导体层和栅电极之间的栅极绝缘层， 其中源电极和漏极各自包括第一导电层，以及具有从第一导电层的端部在沟道长度方向上延伸的区域的第二导电层。

公开(公告)号：US20090111248A1

公开(公告)日：2009-04-30

申请号：US12247487

申请日：2008-10-08

申请人： Hideto OHNUMA ,  Tetsuya KAKEHATA ,  Akihisa SHIMOMURA ,  Shinya SASAGAWA ,  Motomu KURATA

发明人： Hideto OHNUMA ,  Tetsuya KAKEHATA ,  Akihisa SHIMOMURA ,  Shinya SASAGAWA ,  Motomu KURATA

IPC分类号： H01L21/02

CPC分类号： H01L21/76254 ,  H01L21/02532 ,  H01L21/02686 ,  H01L21/268 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/84

摘要： A damaged region is formed by generation of plasma by excitation of a source gas, and by addition of ion species contained in the plasma from one of surfaces of a single crystal semiconductor substrate; an insulating layer is formed over the other surface of the single crystal semiconductor substrate; a supporting substrate is firmly attached to the single crystal semiconductor substrate so as to face the single crystal semiconductor substrate with the insulating layer interposed therebetween; separation is performed at the damaged region into the supporting substrate to which a single crystal semiconductor layer is attached and part of the single crystal semiconductor substrate by heating of the single crystal semiconductor substrate; dry etching is performed on a surface of the single crystal semiconductor layer attached to the supporting substrate; the single crystal semiconductor layer is recrystallized by irradiation of the single crystal semiconductor layer with a laser beam to melt at least part of the single crystal semiconductor layer.

摘要翻译： 通过源气体的激发产生等离子体并通过从单晶半导体衬底的表面之一添加包含在等离子体中的离子种类而形成损伤区域; 在单晶半导体衬底的另一个表面上形成绝缘层; 支撑衬底牢固地附接到单晶半导体衬底，以便在其间插入绝缘层的单晶半导体衬底; 通过加热单晶半导体衬底，在损伤区域处分离成与单晶半导体层相连的支撑衬底和部分单晶半导体衬底; 在附着于支撑基板的单晶半导体层的表面进行干蚀刻， 通过用激光束照射单晶半导体层来使单晶半导体层重结晶，从而熔化至少一部分单晶半导体层。