利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

55 条记录 (耗时 0.034 秒)

    Manufacturing method of SOI substrate
    1.
    发明授权
    Manufacturing method of SOI substrate 有权
    SOI衬底的制造方法

    公开(公告)号：US08828844B2

    公开(公告)日：2014-09-09

    申请号：US12247487

    申请日：2008-10-08

    申请人： Hideto Ohnuma ,  Tetsuya Kakehata ,  Akihisa Shimomura ,  Shinya Sasagawa ,  Motomu Kurata

    发明人： Hideto Ohnuma ,  Tetsuya Kakehata ,  Akihisa Shimomura ,  Shinya Sasagawa ,  Motomu Kurata

    IPC分类号： H01L21/46 ,  H01L21/268 ,  H01L21/3065 ,  H01L21/84 ,  H01L21/02 ,  H01L21/302 ,  H01L21/762

    CPC分类号： H01L21/76254 ,  H01L21/02532 ,  H01L21/02686 ,  H01L21/268 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/84

    摘要： A damaged region is formed by generation of plasma by excitation of a source gas, and by addition of ion species contained in the plasma from one of surfaces of a single crystal semiconductor substrate; an insulating layer is formed over the other surface of the single crystal semiconductor substrate; a supporting substrate is firmly attached to the single crystal semiconductor substrate so as to face the single crystal semiconductor substrate with the insulating layer interposed therebetween; separation is performed at the damaged region into the supporting substrate to which a single crystal semiconductor layer is attached and part of the single crystal semiconductor substrate by heating of the single crystal semiconductor substrate; dry etching is performed on a surface of the single crystal semiconductor layer attached to the supporting substrate; the single crystal semiconductor layer is recrystallized by irradiation of the single crystal semiconductor layer with a laser beam to melt at least part of the single crystal semiconductor layer.

    摘要翻译： 通过源气体的激发产生等离子体并通过从单晶半导体衬底的表面之一添加包含在等离子体中的离子种类而形成损伤区域; 在单晶半导体衬底的另一个表面上形成绝缘层; 支撑衬底牢固地附接到单晶半导体衬底，以便在其间插入绝缘层的单晶半导体衬底; 通过加热单晶半导体衬底，在损伤区域处分离成与单晶半导体层相连的支撑衬底和部分单晶半导体衬底; 在附着于支撑基板的单晶半导体层的表面进行干蚀刻， 通过用激光束照射单晶半导体层来使单晶半导体层重结晶，从而熔化至少一部分单晶半导体层。

    Method for manufacturing SOI substrate
    3.
    发明授权
    Method for manufacturing SOI substrate 有权
    制造SOI衬底的方法

    公开(公告)号：US08383487B2

    公开(公告)日：2013-02-26

    申请号：US13198171

    申请日：2011-08-04

    申请人： Hideomi Suzawa ,  Shinya Sasagawa ,  Akihisa Shimomura ,  Junpei Momo ,  Motomu Kurata ,  Taiga Muraoka ,  Kosei Nei

    发明人： Hideomi Suzawa ,  Shinya Sasagawa ,  Akihisa Shimomura ,  Junpei Momo ,  Motomu Kurata ,  Taiga Muraoka ,  Kosei Nei

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76254

    摘要： Forming an insulating film on a surface of the single crystal semiconductor substrate, forming a fragile region in the single crystal semiconductor substrate by irradiating the single crystal semiconductor substrate with an ion beam through the insulating film, forming a bonding layer over the insulating film, bonding a supporting substrate to the single crystal semiconductor substrate by interposing the bonding layer between the supporting substrate and the single crystal semiconductor substrate, dividing the single crystal semiconductor substrate at the fragile region to separate the single crystal semiconductor substrate into a single crystal semiconductor layer attached to the supporting substrate, performing first dry etching treatment on a part of the fragile region remaining on the single crystal semiconductor layer, performing second dry etching treatment on a surface of the single crystal semiconductor layer subjected to the first etching treatment, and irradiating the single crystal semiconductor layer with laser light.

    摘要翻译： 在单晶半导体基板的表面上形成绝缘膜，在单晶半导体基板中通过用离子束照射单晶半导体基板通过绝缘膜形成脆性区域，在绝缘膜上形成接合层， 通过将支撑基板和单晶半导体基板之间的接合层插入到单晶半导体基板的支撑基板上，将单晶半导体基板分割为脆性区域，将单晶半导体基板分离成单晶半导体层， 所述支撑基板对残留在所述单晶半导体层上的所述易碎区域的一部分进行第一干蚀刻处理，对经过所述第一蚀刻处理的所述单晶半导体层的表面进行第二干蚀刻处理， 具有激光的晶体半导体层。

    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
    5.
    发明申请
    METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE 有权
    制造半导体器件和半导体器件的方法

    公开(公告)号：US20120193625A1

    公开(公告)日：2012-08-02

    申请号：US13357902

    申请日：2012-01-25

    申请人： Shinya SASAGAWA ,  Motomu KURATA

    发明人： Shinya SASAGAWA ,  Motomu KURATA

    IPC分类号： H01L29/786 ,  H01L21/336

    CPC分类号： H01L29/66969 ,  H01L21/441 ,  H01L29/41733 ,  H01L29/7869

    摘要： An object is to provide a semiconductor device in which defects are reduced and miniaturization is achieved while favorable characteristics are maintained. A semiconductor layer is formed; a first conductive layer is formed over the semiconductor layer; the first conductive layer is etched with use of a first resist mask to form a second conductive layer having a recessed portion; the first resist mask is reduced in size to form a second resist mask; the second conductive layer is etched with use of the second resist mask to form source and drain electrodes each having a projecting portion with a tapered shape at the peripheries; a gate insulating layer is formed over the source and drain electrodes to be in contact with part of the semiconductor layer; and a gate electrode is formed in a portion over the gate insulating layer and overlapping with the semiconductor layer.

    摘要翻译： 本发明的目的是提供一种在保持有利特性的同时减小缺陷并实现小型化的半导体器件。 形成半导体层; 在半导体层上形成第一导电层; 使用第一抗蚀剂掩模蚀刻第一导电层以形成具有凹部的第二导电层; 第一抗蚀剂掩模的尺寸减小以形成第二抗蚀剂掩模; 使用第二抗蚀剂掩模蚀刻第二导电层，以形成在周边具有锥形形状的突出部分的源极和漏极; 在源极和漏极上形成栅极绝缘层以与半导体层的一部分接触; 并且栅极电极形成在栅极绝缘层上方并与半导体层重叠的部分。

    THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF
    7.
    发明申请
    THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF 有权
    薄膜晶体管及其制造方法

    公开(公告)号：US20110147745A1

    公开(公告)日：2011-06-23

    申请号：US12973123

    申请日：2010-12-20

    申请人： Shinya SASAGAWA ,  Akihiro ISHIZUKA ,  Shinobu FURUKAWA ,  Motomu KURATA

    发明人： Shinya SASAGAWA ,  Akihiro ISHIZUKA ,  Shinobu FURUKAWA ,  Motomu KURATA

    IPC分类号： H01L29/12 ,  H01L21/20

    CPC分类号： H01L29/66765 ,  H01L29/78669 ,  H01L29/78678 ,  H01L29/78696

    摘要： An embodiment is a thin film transistor which includes a gate electrode layer, a gate insulating layer provided so as to cover the gate electrode layer; a first semiconductor layer entirely overlapped with the gate electrode layer; a second semiconductor layer provided over and in contact with the first semiconductor layer and having a lower carrier mobility than the first semiconductor layer; an impurity semiconductor layer provided in contact with the second semiconductor layer; a sidewall insulating layer provided so as to cover at least a sidewall of the first semiconductor layer; and a source and drain electrode layers provided in contact with at least the impurity semiconductor layer. The second semiconductor layer may consist of parts which are apart from each other over the first semiconductor layer.

    摘要翻译： 一个实施例是一种薄膜晶体管，其包括栅极电极层，设置为覆盖栅极电极层的栅极绝缘层; 与栅电极层完全重叠的第一半导体层; 第二半导体层，设置在第一半导体层上并与第一半导体层接触，并具有比第一半导体层低的载流子迁移率; 设置成与所述第二半导体层接触的杂质半导体层; 侧壁绝缘层，设置成覆盖所述第一半导体层的至少一个侧壁; 以及与至少所述杂质半导体层接触地设置的源极和漏极电极层。 第二半导体层可以由在第一半导体层上彼此分开的部分组成。

    METHOD FOR MANUFACTURING SOI SUBSTRATE
    9.
    发明申请
    METHOD FOR MANUFACTURING SOI SUBSTRATE 有权
    制造SOI衬底的方法

    公开(公告)号：US20090239354A1

    公开(公告)日：2009-09-24

    申请号：US12399047

    申请日：2009-03-06

    申请人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Akihisa SHIMOMURA ,  Junpei MOMO ,  Motomu KURATA ,  Taiga MURAOKA ,  Kosei NEI

    发明人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Akihisa SHIMOMURA ,  Junpei MOMO ,  Motomu KURATA ,  Taiga MURAOKA ,  Kosei NEI

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76254

    摘要： Forming an insulating film on a surface of the single crystal semiconductor substrate, forming a fragile region in the single crystal semiconductor substrate by irradiating the single crystal semiconductor substrate with an ion beam through the insulating film, forming a bonding layer over the insulating film, bonding a supporting substrate to the single crystal semiconductor substrate by interposing the bonding layer between the supporting substrate and the single crystal semiconductor substrate, dividing the single crystal semiconductor substrate at the fragile region to separate the single crystal semiconductor substrate into a single crystal semiconductor layer attached to the supporting substrate, performing first dry etching treatment on a part of the fragile region remaining on the single crystal semiconductor layer, performing second dry etching treatment on a surface of the single crystal semiconductor layer subjected to the first etching treatment, and irradiating the single crystal semiconductor layer with laser light.

    摘要翻译： 在单晶半导体基板的表面上形成绝缘膜，在单晶半导体基板中通过用离子束照射单晶半导体基板通过绝缘膜形成脆性区域，在绝缘膜上形成接合层， 通过将支撑基板和单晶半导体基板之间的接合层插入到单晶半导体基板的支撑基板上，将单晶半导体基板分割为脆性区域，将单晶半导体基板分离成单晶半导体层， 所述支撑基板对残留在所述单晶半导体层上的所述脆性区域的一部分进行第一干蚀刻处理，对经过所述第一蚀刻处理的所述单晶半导体层的表面进行第二干蚀刻处理， 具有激光的晶体半导体层。

    Method for manufacturing semiconductor device and semiconductor device
    10.
    发明授权
    Method for manufacturing semiconductor device and semiconductor device 有权
    半导体器件和半导体器件的制造方法

    公开(公告)号：US08987727B2

    公开(公告)日：2015-03-24

    申请号：US13357902

    申请日：2012-01-25

    申请人： Shinya Sasagawa ,  Motomu Kurata

    发明人： Shinya Sasagawa ,  Motomu Kurata

    IPC分类号： H01L29/786 ,  H01L21/34 ,  H01L29/417

    CPC分类号： H01L29/66969 ,  H01L21/441 ,  H01L29/41733 ,  H01L29/7869

    摘要： An object is to provide a semiconductor device in which defects are reduced and miniaturization is achieved while favorable characteristics are maintained. A semiconductor layer is formed; a first conductive layer is formed over the semiconductor layer; the first conductive layer is etched with use of a first resist mask to form a second conductive layer having a recessed portion; the first resist mask is reduced in size to form a second resist mask; the second conductive layer is etched with use of the second resist mask to form source and drain electrodes each having a projecting portion with a tapered shape at the peripheries; a gate insulating layer is formed over the source and drain electrodes to be in contact with part of the semiconductor layer; and a gate electrode is formed in a portion over the gate insulating layer and overlapping with the semiconductor layer.

    摘要翻译： 本发明的目的是提供一种在保持有利特性的同时减小缺陷并实现小型化的半导体器件。 形成半导体层; 在半导体层上形成第一导电层; 使用第一抗蚀剂掩模蚀刻第一导电层以形成具有凹部的第二导电层; 第一抗蚀剂掩模的尺寸减小以形成第二抗蚀剂掩模; 使用第二抗蚀剂掩模蚀刻第二导电层，以形成在周边具有锥形形状的突出部分的源极和漏极; 在源极和漏极上形成栅极绝缘层以与半导体层的一部分接触; 并且栅极电极形成在栅极绝缘层上方并与半导体层重叠的部分。