公开(公告)号：US20110180796A1

公开(公告)日：2011-07-28

申请号：US13008285

申请日：2011-01-18

申请人： Shunpei YAMAZAKI ,  Hiromichi GODO ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Motomu KURATA ,  Mayumi MIKAMI

发明人： Shunpei YAMAZAKI ,  Hiromichi GODO ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Motomu KURATA ,  Mayumi MIKAMI

IPC分类号： H01L29/24

CPC分类号： H01L29/7869

摘要： An object is to provide a semiconductor device including an oxide semiconductor, which maintains favorable characteristics and achieves miniaturization. The semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode in contact with the oxide semiconductor layer, a gate electrode overlapping with the oxide semiconductor layer, and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode, in which the source electrode and the drain electrode each include a first conductive layer, and a second conductive layer having a region which extends in a channel length direction from an end portion of the first conductive layer.

摘要翻译： 本发明的目的是提供一种包含氧化物半导体的半导体器件，其保持有利的特性并实现小型化。 半导体器件包括与氧化物半导体层接触的氧化物半导体层，源极和漏电极，与氧化物半导体层重叠的栅电极，以及设置在氧化物半导体层和栅电极之间的栅极绝缘层， 其中源电极和漏极各自包括第一导电层，以及具有从第一导电层的端部在沟道长度方向上延伸的区域的第二导电层。

公开(公告)号：US20110193080A1

公开(公告)日：2011-08-11

申请号：US13014081

申请日：2011-01-26

申请人： Shunpei YAMAZAKI ,  Hiromichi GODO ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Motomu KURATA ,  Mayumi MIKAMI

发明人： Shunpei YAMAZAKI ,  Hiromichi GODO ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Motomu KURATA ,  Mayumi MIKAMI

IPC分类号： H01L29/78

CPC分类号： H01L29/7869 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/66969 ,  Y10T428/24421

摘要： One object is to provide a semiconductor device that includes an oxide semiconductor and is reduced in size with favorable characteristics maintained. The semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode in contact with the oxide semiconductor layer, a gate electrode overlapping with the oxide semiconductor layer; and a gate insulating layer between the oxide semiconductor layer and the gate electrode. The source electrode or the drain electrode includes a first conductive layer and a second conductive layer having a region extended in a channel length direction from an end face of the first conductive layer. The sidewall insulating layer has a length of a bottom surface in the channel length direction smaller than a length in the channel length direction of the extended region of the second conductive layer and is provided over the extended region.

摘要翻译： 一个目的是提供一种包括氧化物半导体的半导体器件，并且尺寸减小，并保持良好的特性。 半导体器件包括与氧化物半导体层接触的氧化物半导体层，源电极和漏电极，与氧化物半导体层重叠的栅电极; 以及在氧化物半导体层和栅电极之间的栅极绝缘层。 源电极或漏极包括第一导电层和具有从第一导电层的端面在沟道长度方向上延伸的区域的第二导电层。 侧壁绝缘层的沟道长度方向的底面的长度小于第二导电层的延伸区域的沟道长度方向的长度，并且设置在延伸区域上。

公开(公告)号：US20100283105A1

公开(公告)日：2010-11-11

申请号：US12840442

申请日：2010-07-21

申请人： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Motomu KURATA

发明人： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Motomu KURATA

IPC分类号： H01L29/786

CPC分类号： H01L29/41733 ,  H01L21/76804 ,  H01L21/76805 ,  H01L23/485 ,  H01L27/124 ,  H01L2924/0002 ,  H01L2924/00

摘要： A technique of manufacturing a semiconductor device in which etching in formation of a contact hole can be easily controlled is proposed. A semiconductor device includes at least a semiconductor layer formed over an insulating surface; a first insulating layer formed over the semiconductor layer; a gate electrode formed over the first insulating layer; a second insulating layer formed over the gate electrode; and a conductive layer formed over the second insulating layer connected to the semiconductor layer via an opening which is formed at least in the semiconductor layer and the second insulating layer and partially exposes the insulating surface. The conductive layer is electrically connected to the semiconductor layer at the side surface of the opening which is formed in the semiconductor layer.

摘要翻译： 提出了可以容易地控制形成接触孔的蚀刻的半导体器件的制造技术。 半导体器件至少包括形成在绝缘表面上的半导体层; 形成在所述半导体层上的第一绝缘层; 形成在所述第一绝缘层上的栅电极; 形成在所述栅电极上的第二绝缘层; 以及形成在所述第二绝缘层之上的导电层，所述导电层经由至少在所述半导体层和所述第二绝缘层中形成并且部分地暴露所述绝缘表面的开口连接到所述半导体层。 导电层在形成于半导体层的开口的侧面与半导体层电连接。

公开(公告)号：US20080237875A1

公开(公告)日：2008-10-02

申请号：US12046817

申请日：2008-03-12

申请人： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Motomu KURATA

发明人： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Motomu KURATA

IPC分类号： H01L23/52 ,  H01L21/28

CPC分类号： H01L29/41733 ,  H01L21/76804 ,  H01L21/76805 ,  H01L23/485 ,  H01L27/124 ,  H01L2924/0002 ,  H01L2924/00

摘要： A technique of manufacturing a semiconductor device in which etching in formation of a contact hole can be easily controlled is proposed. A semiconductor device includes at least a semiconductor layer formed over an insulating surface; a first insulating layer formed over the semiconductor layer; a gate electrode formed over the first insulating layer; a second insulating layer formed over the gate electrode; and a conductive layer formed over the second insulating layer connected to the semiconductor layer via an opening which is formed at least in the semiconductor layer and the second insulating layer and partially exposes the insulating surface. The conductive layer is electrically connected to the semiconductor layer at the side surface of the opening which is formed in the semiconductor layer.

摘要翻译： 提出了可以容易地控制形成接触孔的蚀刻的半导体器件的制造技术。 半导体器件至少包括形成在绝缘表面上的半导体层; 形成在所述半导体层上的第一绝缘层; 形成在所述第一绝缘层上的栅电极; 形成在所述栅电极上的第二绝缘层; 以及形成在所述第二绝缘层之上的导电层，所述导电层经由至少在所述半导体层和所述第二绝缘层中形成并且部分地暴露所述绝缘表面的开口连接到所述半导体层。 导电层在形成于半导体层的开口的侧面与半导体层电连接。

公开(公告)号：US20090239354A1

公开(公告)日：2009-09-24

申请号：US12399047

申请日：2009-03-06

申请人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Akihisa SHIMOMURA ,  Junpei MOMO ,  Motomu KURATA ,  Taiga MURAOKA ,  Kosei NEI

发明人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Akihisa SHIMOMURA ,  Junpei MOMO ,  Motomu KURATA ,  Taiga MURAOKA ,  Kosei NEI

IPC分类号： H01L21/762

CPC分类号： H01L21/76254

摘要： Forming an insulating film on a surface of the single crystal semiconductor substrate, forming a fragile region in the single crystal semiconductor substrate by irradiating the single crystal semiconductor substrate with an ion beam through the insulating film, forming a bonding layer over the insulating film, bonding a supporting substrate to the single crystal semiconductor substrate by interposing the bonding layer between the supporting substrate and the single crystal semiconductor substrate, dividing the single crystal semiconductor substrate at the fragile region to separate the single crystal semiconductor substrate into a single crystal semiconductor layer attached to the supporting substrate, performing first dry etching treatment on a part of the fragile region remaining on the single crystal semiconductor layer, performing second dry etching treatment on a surface of the single crystal semiconductor layer subjected to the first etching treatment, and irradiating the single crystal semiconductor layer with laser light.

摘要翻译： 在单晶半导体基板的表面上形成绝缘膜，在单晶半导体基板中通过用离子束照射单晶半导体基板通过绝缘膜形成脆性区域，在绝缘膜上形成接合层， 通过将支撑基板和单晶半导体基板之间的接合层插入到单晶半导体基板的支撑基板上，将单晶半导体基板分割为脆性区域，将单晶半导体基板分离成单晶半导体层， 所述支撑基板对残留在所述单晶半导体层上的所述脆性区域的一部分进行第一干蚀刻处理，对经过所述第一蚀刻处理的所述单晶半导体层的表面进行第二干蚀刻处理， 具有激光的晶体半导体层。

公开(公告)号：US20110287605A1

公开(公告)日：2011-11-24

申请号：US13198171

申请日：2011-08-04

申请人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Akihisa SHIMOMURA ,  Junpei MOMO ,  Motomu KURATA ,  Taiga MURAOKA ,  Kosei NEI

发明人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Akihisa SHIMOMURA ,  Junpei MOMO ,  Motomu KURATA ,  Taiga MURAOKA ,  Kosei NEI

IPC分类号： H01L21/762

CPC分类号： H01L21/76254

摘要： Forming an insulating film on a surface of the single crystal semiconductor substrate, forming a fragile region in the single crystal semiconductor substrate by irradiating the single crystal semiconductor substrate with an ion beam through the insulating film, forming a bonding layer over the insulating film, bonding a supporting substrate to the single crystal semiconductor substrate by interposing the bonding layer between the supporting substrate and the single crystal semiconductor substrate, dividing the single crystal semiconductor substrate at the fragile region to separate the single crystal semiconductor substrate into a single crystal semiconductor layer attached to the supporting substrate, performing first dry etching treatment on a part of the fragile region remaining on the single crystal semiconductor layer, performing second dry etching treatment on a surface of the single crystal semiconductor layer subjected to the first etching treatment, and irradiating the single crystal semiconductor layer with laser light.

摘要翻译： 在单晶半导体基板的表面上形成绝缘膜，在单晶半导体基板中通过用离子束照射单晶半导体基板通过绝缘膜形成脆性区域，在绝缘膜上形成接合层， 通过将支撑基板和单晶半导体基板之间的接合层插入到单晶半导体基板的支撑基板上，将单晶半导体基板分割为脆性区域，将单晶半导体基板分离成单晶半导体层， 所述支撑基板对残留在所述单晶半导体层上的所述脆性区域的一部分进行第一干蚀刻处理，对经过所述第一蚀刻处理的所述单晶半导体层的表面进行第二干蚀刻处理， 具有激光的晶体半导体层。

公开(公告)号：US20110210326A1

公开(公告)日：2011-09-01

申请号：US13029146

申请日：2011-02-17

申请人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Motomu KURATA

发明人： Hideomi SUZAWA ,  Shinya SASAGAWA ,  Motomu KURATA

IPC分类号： H01L29/78

CPC分类号： H01L29/7869 ,  G11C16/0408 ,  G11C16/0483 ,  H01L27/11521 ,  H01L27/1156 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/66969

摘要： A semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode in contact with the oxide semiconductor layer, a gate electrode overlapping with the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate electrode, in which the source electrode or the drain electrode comprises a first conductive layer and a second conductive layer having a region which extends beyond an end portion of the first conductive layer in a channel length direction and which overlaps with part of the gate electrode, in which a sidewall insulating layer is provided over the extended region of the second conductive layer, and in which the sidewall insulating layer comprises a stack of a plurality of different material layers.

摘要翻译： 半导体器件包括与氧化物半导体层接触的氧化物半导体层，源电极和漏电极，与氧化物半导体层重叠的栅电极，以及在氧化物半导体层和栅电极之间的栅极绝缘层， 源电极或漏电极包括第一导电层和第二导电层，第二导电层具有在沟道长度方向上延伸超出第一导电层的端部并且与栅电极的一部分重叠的区域，其中 侧壁绝缘层设置在第二导电层的延伸区域上，并且其中侧壁绝缘层包括多个不同材料层的堆叠。

公开(公告)号：US20110254004A1

公开(公告)日：2011-10-20

申请号：US13168673

申请日：2011-06-24

申请人： Shunpei YAMAZAKI ,  Kazuko IKEDA ,  Shinya SASAGAWA ,  Hideomi SUZAWA

发明人： Shunpei YAMAZAKI ,  Kazuko IKEDA ,  Shinya SASAGAWA ,  Hideomi SUZAWA

IPC分类号： H01L29/04 ,  H01L29/786

CPC分类号： H01L29/4908 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78609

摘要： A semiconductor device manufactured utilizing an SOI substrate, in which defects due to an end portion of an island-shaped silicon layer are prevented and the reliability is improved, and a manufacturing method thereof. The following are included: an SOI substrate in which an insulating layer and an island-shaped silicon layer are stacked in order over a support substrate; a gate insulating layer provided over one surface and a side surface of the island-shaped silicon layer; and a gate electrode which is provided over the island-shaped silicon layer with the gate insulating layer interposed therebetween. The gate insulating layer is formed such that the dielectric constant in the region which is in contact with the side surface of the island-shaped silicon layer is lower than that over the one surface of the island-shaped silicon layer.

摘要翻译： 利用SOI衬底制造的半导体器件及其制造方法，其中防止了由岛状硅层的端部引起的缺陷并提高了可靠性。 包括以下：SOI基板，其中绝缘层和岛状硅层依次层叠在支撑基板上; 设置在岛状硅层的一个表面和侧面上的栅极绝缘层; 以及栅极电极，其设置在岛状硅层上，栅极绝缘层插入其间。 栅极绝缘层形成为与岛状硅层的侧面接触的区域的介电常数低于岛状硅层的一个表面的介电常数。

公开(公告)号：US20110287580A1

公开(公告)日：2011-11-24

申请号：US13107054

申请日：2011-05-13

申请人： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Shinya SASAGAWA

发明人： Shunpei YAMAZAKI ,  Hideomi SUZAWA ,  Shinya SASAGAWA

IPC分类号： H01L21/336

CPC分类号： H01L29/7869 ,  H01L27/1225 ,  H01L29/66969

摘要： An object of an embodiment of the present invention is to provide a semiconductor device including a normally-off oxide semiconductor element whose characteristic variation is small in the long term. A cation containing one or more elements selected from oxygen and halogen is added to an oxide semiconductor layer, thereby suppressing elimination of oxygen, reducing hydrogen, or suppressing movement of hydrogen. Accordingly, carriers in the oxide semiconductor can be reduced and the number of the carriers can be kept constant in the long term. As a result, the semiconductor device including the normally-off oxide semiconductor element whose characteristic variation is small in the long term can be provided.

摘要翻译： 本发明的一个实施例的目的是提供一种包括其长期特性变化小的常关氧化物半导体元件的半导体器件。 将含有选自氧和卤素的一种或多种元素的阳离子加入到氧化物半导体层中，从而抑制氧的消除，还原氢或抑制氢的移动。 因此，可以减少氧化物半导体中的载流子，并且可以长期保持载流子的数量恒定。 结果，可以提供包括其长期特性变化小的常关氧化物半导体元件的半导体器件。

公开(公告)号：US20120187397A1

公开(公告)日：2012-07-26

申请号：US13356012

申请日：2012-01-23

申请人： Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Toshihiko SAITO ,  Takehisa HATANO ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Junichi KOEZUKA ,  Yuichi SATO ,  Shinji OHNO

发明人： Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Toshihiko SAITO ,  Takehisa HATANO ,  Hideomi SUZAWA ,  Shinya SASAGAWA ,  Junichi KOEZUKA ,  Yuichi SATO ,  Shinji OHNO

IPC分类号： H01L29/786

CPC分类号： H01L29/66969 ,  H01L21/02488 ,  H01L21/02565 ,  H01L27/1225 ,  H01L29/786 ,  H01L29/78606 ,  H01L29/7869

摘要： A semiconductor device which includes an oxide semiconductor and has favorable electrical characteristics is provided. In the semiconductor device, an oxide semiconductor film and an insulating film are formed over a substrate. Side surfaces of the oxide semiconductor film are in contact with the insulating film. The oxide semiconductor film includes a channel formation region and regions containing a dopant between which the channel formation region is sandwiched. A gate insulating film is formed on and in contact with the oxide semiconductor film. A gate electrode with sidewall insulating films is formed over the gate insulating film. A source electrode and a drain electrode are formed in contact with the oxide semiconductor film and the insulating film.

摘要翻译： 提供了包括氧化物半导体并且具有良好的电特性的半导体器件。 在半导体器件中，在衬底上形成氧化物半导体膜和绝缘膜。 氧化物半导体膜的侧面与绝缘膜接触。 氧化物半导体膜包括沟道形成区域和包含掺杂剂的区域，沟道形成区域夹在其间。 栅极绝缘膜与氧化物半导体膜形成并接触。 在栅绝缘膜上形成具有侧壁绝缘膜的栅电极。 源电极和漏电极形成为与氧化物半导体膜和绝缘膜接触。