公开(公告)号：US20110068339A1

公开(公告)日：2011-03-24

申请号：US12958739

申请日：2010-12-02

申请人： Toshimitsu KONUMA ,  Akira SUGAWARA ,  Yukiko UEHARA ,  Hongyong ZHANG ,  Atsunori SUZUKI ,  Hideto OHNUMA ,  Naoaki YAMAGUCHI ,  Hideomi SUZAWA ,  Hideki UOCHI ,  Yasuhiko TAKEMURA

发明人： Toshimitsu KONUMA ,  Akira SUGAWARA ,  Yukiko UEHARA ,  Hongyong ZHANG ,  Atsunori SUZUKI ,  Hideto OHNUMA ,  Naoaki YAMAGUCHI ,  Hideomi SUZAWA ,  Hideki UOCHI ,  Yasuhiko TAKEMURA

IPC分类号： H01L29/772 ,  H01L27/12

CPC分类号： H01L29/665 ,  H01L21/02145 ,  H01L21/02244 ,  H01L21/02258 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/31683 ,  H01L21/31687 ,  H01L21/321 ,  H01L27/124 ,  H01L27/127 ,  H01L29/458 ,  H01L29/66598 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627

摘要： A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in order to reduce an Ioff current. A method for forming this structure comprises the steps of anodizing the gate electrode to form a porous anodic oxide film on the side of the gate electrode; removing a portion of the gate insulating using the porous anodic oxide film as a mask so that the gate insulating film extends beyond the gate electrode but does not completely cover the source and drain regions. Thereafter, an ion doping of one conductivity element is performed. The high resistivity region is defined under the gate insulating film.

摘要翻译： 形成在绝缘基板源极，漏极和沟道区上的TFT，至少形成在沟道区上的栅极绝缘膜和形成在栅极绝缘膜上的栅电极。 在沟道区域和漏极区域之间，提供具有较高电阻率的区域以便减小偏转电流。 形成该结构的方法包括以下步骤：在栅电极侧阳极氧化栅电极以形成多孔阳极氧化膜; 使用多孔阳极氧化膜去除一部分栅极绝缘体作为掩模，使得栅极绝缘膜延伸超过栅极电极但不完全覆盖源极和漏极区域。 此后，进行一个导电性元素的离子掺杂。 高电阻率区域限定在栅极绝缘膜下。

公开(公告)号：US20100068860A1

公开(公告)日：2010-03-18

申请号：US12621537

申请日：2009-11-19

申请人： Hongyong ZHANG ,  Yasuhiko TAKEMURA ,  Toshimitsu KONUMA ,  Hideto OHNUMA ,  Naoaki YAMAGUCHI ,  Hideomi SUZAWA ,  Hideki UOCHI

发明人： Hongyong ZHANG ,  Yasuhiko TAKEMURA ,  Toshimitsu KONUMA ,  Hideto OHNUMA ,  Naoaki YAMAGUCHI ,  Hideomi SUZAWA ,  Hideki UOCHI

IPC分类号： H01L21/336

CPC分类号： H01L27/127 ,  H01L27/1214 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627

摘要： There is provided a method by which lightly doped drain (LDD) regions can be formed easily and at good yields in source/drain regions in thin film transistors possessing gate electrodes covered with an oxide covering. A lightly doped drain (LDD) region is formed by introducing an impurity into an island-shaped silicon film in a self-aligning manner, with a gate electrode serving as a mask. First, low-concentration impurity regions are formed in the island-shaped silicon film by using rotation-tilt ion implantation to effect ion doping from an oblique direction relative to the substrate. Low-concentration impurity regions are also formed below the gate electrode at this time. After that, an impurity at a high concentration is introduced normally to the substrate, so forming high-concentration impurity regions. In the above process, a low-concentration impurity region remains below the gate electrode and constitutes a lightly doped drain region.

摘要翻译： 提供了一种方法，通过该方法可以容易地形成轻掺杂漏极（LDD）区域，并且在具有覆盖有氧化物覆盖层的栅电极的薄膜晶体管中的源/漏区域中以良好的产率形成。 通过以栅极电极作为掩模，以自对准的方式将杂质引入岛状硅膜中形成轻掺杂漏极（LDD）区域。 首先，通过使用旋转 - 倾斜离子注入在岛状硅膜中形成低浓度杂质区，以相对于衬底从倾斜方向进行离子掺杂。 此时也在栅电极下方形成低浓度杂质区。 之后，将高浓度的杂质通常引入衬底，从而形成高浓度杂质区域。 在上述过程中，低浓度杂质区域保留在栅电极下方并构成轻掺杂漏区。