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8 条记录 (耗时 0.016 秒)

    Analog-to-digital converter
    1.
    发明授权
    Analog-to-digital converter 失效
    模数转换器

    公开(公告)号：US4368457A

    公开(公告)日：1983-01-11

    申请号：US887966

    申请日：1978-03-20

    申请人： Toshiro Tsukada ,  Hisashi Tsuruoka ,  Michio Hara

    发明人： Toshiro Tsukada ,  Hisashi Tsuruoka ,  Michio Hara

    IPC分类号： H03M1/54 ,  H03M1/00 ,  H03K13/20

    CPC分类号： H03M1/1295

    摘要： An analog-to-digital converter comprising a capacitive element for storing an analog input signal, a discharge means for discharging the charge stored in said capacitive element, a means for counting the number of clockpulses between the time of discharge starting and the time at which the voltage at the output of said capacitive element reaches a certain detection level, and a bias voltage supply means for supplying a bias voltage in order to bring the voltage at the output terminal of said capacitive element at the discharge starting time above said detection level.

    摘要翻译： 一种模数转换器，包括用于存储模拟输入信号的电容元件，用于放电存储在所述电容元件中的电荷的放电装置，用于对放电起始时间之间的时钟脉冲数进行计数的装置， 所述电容元件的输出端的电压达到一定的检测电平;以及偏置电压供给装置，用于提供偏置电压，以使所述电容元件的输出端处的电压处于高于所述检测电平的放电开始时间。

    Analog-to-digital converter
    2.
    发明授权
    Analog-to-digital converter 失效
    模数转换器

    公开(公告)号：US4178585A

    公开(公告)日：1979-12-11

    申请号：US935963

    申请日：1978-08-22

    申请人： Katsuaki Takagi ,  Toshiro Tsukada ,  Hisashi Tsuruoka ,  Michio Hara

    发明人： Katsuaki Takagi ,  Toshiro Tsukada ,  Hisashi Tsuruoka ,  Michio Hara

    IPC分类号： H03M1/54 ,  H03M1/00 ,  H03K13/20

    CPC分类号： H03M1/403

    摘要： An analog-to-digital converter comprising a capacitor for storing an analog input signal, a constant current discharging circuit coupled with the capacitor for discharging the charge stored therein, a level detection circuit connected to the input terminal of the capacitor, a counter connected to the output terminal of the level detection circuit for counting the number of clock-pulses between the time of discharge start and the time when the voltage at the input terminal of the capacitor drops to a detection level of the level detection circuit, a bias voltage supply means connected in series with the capacitor for adding a bias voltage to the voltage at the input terminal of said capacitor, and a switch connected in parallel with the capacitor for short-circuiting the capacitor when the voltage at the input terminal of said capacitor drops to the detection level.

    摘要翻译： 一种模数转换器，包括用于存储模拟输入信号的电容器，与电容器耦合的恒流放电电路，用于对存储在其中的电荷进行放电;电平检测电路，连接到电容器的输入端;计数器，连接到 用于对放电开始时间之间的时钟脉冲数进行计数的电平检测电路的输出端与电容器的输入端的电压下降到电平检测电路的检测电平的时间之间;偏置电压源 与电容器串联连接的装置，用于向所述电容器的输入端子处的电压增加偏置电压，以及当电容器的输入端子处的电压下降到电容器时与电容器并联连接的开关，用于使电容器短路 检测水平。

    Analog-to-digital converter employing constant-current circuit incorporating MISFET
    3.
    发明授权
    Analog-to-digital converter employing constant-current circuit incorporating MISFET 失效
    采用集成MISFET的恒流电路的模数转换器

    公开(公告)号：US4250493A

    公开(公告)日：1981-02-10

    申请号：US925790

    申请日：1978-07-18

    申请人： Toshimasa Kihara ,  Toshiro Tsukada

    发明人： Toshimasa Kihara ,  Toshiro Tsukada

    IPC分类号： F02D41/24 ,  G05F3/24 ,  H03M1/00 ,  H03K13/02

    CPC分类号： F02D41/28 ,  G05F3/242 ,  H03M1/345

    摘要： The constant-current circuit consists of two MISFETs connected in series and a gate bias circuit for these MISFETs. The drain voltage of the first MISFET is maintained substantially constant by the source voltage of the second MISFET. The first MISFET does not sustain the channel length modulation, because its drain voltage is substantially constant. Consequently, a constant output current is obtained through the drain of the second MISFET.

    摘要翻译： 恒流电路由串联连接的两个MISFET和这些MISFET的栅极偏置电路组成。 第一MISFET的漏极电压由第二MISFET的源极电压基本上保持恒定。 因为漏极电压基本上是恒定的，所以第一MISFET不支持沟道长度调制。 因此，通过第二MISFET的漏极获得恒定的输出电流。

    Digital video signal processor
    4.
    发明授权
    Digital video signal processor 失效
    数字视频信号处理器

    公开(公告)号：US4825287A

    公开(公告)日：1989-04-25

    申请号：US063476

    申请日：1987-06-18

    申请人： Toru Baji ,  Tatsuji Matsuura ,  Toshiro Tsukada ,  Shinya Ohba

    发明人： Toru Baji ,  Tatsuji Matsuura ,  Toshiro Tsukada ,  Shinya Ohba

    IPC分类号： H04N5/14

    CPC分类号： H04N5/14

    摘要： According to the present invention, the number of elements of a signal processing circuit or the like can be drastically reduced by conducting a time-multiplex processing. In a transversal filter having a coefficient of symmetry of 16 taps, for example, the prior art requires about 58,000 transistors. In case four signal processing cores (i.e., SPC) having a function of four taps are used, the number of transistors required can be reduced to about 34,000 by a duplexing process. In case two SPCs having a function of eight taps are used, the number can be reduced to about 19,000 by a quadplexing process. In case, moreover, one SPC having a function of sixteen taps is used, the number can be reduced to about 13,000 by an octaplexing process. Here, the reason why the number of elements is not halved even if the number of the SPCs is halved is that the number of elements to be used in control circuits, memories and so on increases.

    摘要翻译： 根据本发明，通过进行时间复用处理，可以大大减少信号处理电路等的元件数量。 在具有16个抽头的对称系数的横向滤波器中，例如，现有技术需要约58,000个晶体管。 在使用具有四个抽头功能的四个信号处理核心（即，SPC）的情况下，通过双工处理，所需的晶体管数量可以减少到约34,000个。 在使用具有八个抽头功能的两个SPC的情况下，通过四重处理可将数量减少到约19,000个。 此外，在使用具有十六个抽头功能的一个SPC的情况下，也可以通过八次打印处理将数量减少到约13,000个。 这里，即使SPC的数量减半，元件的数量不减半的原因在于控制电路，存储器等中要使用的元件的数量增加。

    Voltage comparator
    7.
    发明授权
    Voltage comparator 失效
    电压比较器

    公开(公告)号：US5113090A

    公开(公告)日：1992-05-12

    申请号：US574087

    申请日：1990-08-29

    申请人： Eiki Imaizumi ,  Kunihiko Usui ,  Tatsuji Matsuura ,  Toshiro Tsukada ,  Seiichi Ueda ,  Hiroshi Sato

    发明人： Eiki Imaizumi ,  Kunihiko Usui ,  Tatsuji Matsuura ,  Toshiro Tsukada ,  Seiichi Ueda ,  Hiroshi Sato

    IPC分类号： H03M1/34 ,  H03K5/08 ,  H03K5/24

    CPC分类号： H03K5/2481

    摘要： A voltage comparator is provided including a differential amplifier, first, second and third switches, and first and second capacitors. A fourth switch is connected in series between the second and third switches and an input terminal of the differential amplifier. A first input voltage is sampled and held at the first capacitor through the first switch and at the second capacitor through the second and fourth switches, respectively. Thereafter, since the third switch is turned on and the fourth switch is turned off, the first input voltage is sampled and held at the input capacitor of the differential amplifier. Thereafter, the third switch is turned off and the fourth switch turned on. As a result, an on and off operation of the fourth switch is controlled so that a second input voltage which has been sampled at the second capacitor immediately before the switch is turned off is applied to the input capacitor of the differential amplifier.

    摘要翻译： 提供电压比较器，其包括差分放大器，第一，第二和第三开关以及第一和第二电容器。 第四开关串联连接在第二和第三开关和差分放大器的输入端之间。 第一输入电压通过第一开关和第二电容器分别通过第二和第四开关被采样并保持在第一电容器处。 此后，由于第三开关导通，第四开关断开，所以第一输入电压被采样并保持在差分放大器的输入电容器。 此后，第三开关断开，第四开关导通。 结果，控制第四开关的接通和断开操作，使得在开关断开之前在第二电容器处被采样的第二输入电压被施加到差分放大器的输入电容器。