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    COMPLEX BANDPASS DELTASIGMAAD MODULATOR AND DIGITAL RADIO RECEIVER
    1.
    发明申请
    COMPLEX BANDPASS DELTASIGMAAD MODULATOR AND DIGITAL RADIO RECEIVER 有权
    复合BANDPASS DELTASIGMAAD调制器和数字无线电接收器

    公开(公告)号：US20110316729A1

    公开(公告)日：2011-12-29

    申请号：US13254333

    申请日：2010-02-24

    申请人： Hao San ,  Haruo Kobayashi

    发明人： Hao San ,  Haruo Kobayashi

    IPC分类号： H03M3/02

    CPC分类号： H03M3/368 ,  H03M3/40

    摘要： To provide a complex bandpass ΔΣAD modulator capable of suppressing the influence of an image component caused by a mismatch between I- and Q-channels on a signal component with low power consumption.A complex bandpass READ modulator 10 is configured by a subtraction unit 20, a complex bandpass filter 30, an addition unit 40, a noise extraction circuit unit 50, an ADC unit 60, and a DAC unit 70. The noise extraction circuit unit 50 extracts a quantized noise signal of the ADC unit 60 based on an input signal of the ADC unit 60 and an output signal of the DAC unit 70, delays the extracted quantized noise signal by one sample time, phase-rotates the delayed signal by a predetermined angle, and feeds back the rotated signal to the input side of the ADC unit 60. Thus, a complex bandpass ΔΣAD modulator capable of suppressing the influence of the image component caused by a mismatch between I- and Q-channels on the signal component with low power consumption is provided.

    摘要翻译： 提供一种复杂的带通＆Dgr＆amp; AD调制器，其能够抑制由于具有低功耗的信号分量上的I通道和Q通道之间的失配引起的图像分量的影响。 复数带通读调制器10由减法单元20，复带通滤波器30，加法单元40，噪声提取电路单元50，ADC单元60和DAC单元70构成。噪声提取电路单元50提取 基于ADC单元60的输入信号和DAC单元70的输出信号的ADC单元60的量化噪声信号将所提取的量化噪声信号延迟一个采样时间，将延迟信号相位旋转预定角度 ，并将旋转的信号反馈到ADC单元60的输入侧。因此，能够抑制由I和Q通道之间的失配引起的图像分量对该影像分量的影响的复数带通＆Dgr＆amp; 提供低功耗的信号分量。

    High-precision multi-band pass ΔΣ modulator
    2.
    发明授权
    High-precision multi-band pass ΔΣ modulator 失效
    高精度多通道DeltaSigma调制器

    公开(公告)号：US07629911B2

    公开(公告)日：2009-12-08

    申请号：US12096021

    申请日：2006-08-01

    申请人： Hiroyuki Hagiwara ,  Atsushi Motozawa ,  Haruo Kobayashi ,  Hao San

    发明人： Hiroyuki Hagiwara ,  Atsushi Motozawa ,  Haruo Kobayashi ,  Hao San

    IPC分类号： H03M3/00

    CPC分类号： H03M1/0665 ,  H03M1/74 ,  H03M3/338 ,  H03M3/424 ,  H03M3/464

    摘要： A high-precision ΔΣ modulator reduces nonlinear noise due to the use of a multibit DAC and has little hardware and power consumption. A digital signal is DA converted and fed back to a subtraction circuit supplied with an analog signal. The DAC used in this feedback circuit uses a DAC (DWADAC) that includes a weighted pointer so that input digital signals are supplied in order to a plurality of segment elements that construct the DAC. In this DWADAC, the construction and number of the pointer is set based on the type and order of the filter disposed before the ADC.

    摘要翻译： 高精度DeltaSigma调制器由于使用多位DAC而降低了非线性噪声，几乎没有硬件和功耗。 数字信号被DA转换并反馈到提供有模拟信号的减法电路。 在该反馈电路中使用的DAC使用包括加权指针的DAC（DWADAC），以便为构成DAC的多个段元件提供输入数字信号。 在这个DWADAC中，指针的构造和数量是根据ADC之前设置的滤波器的类型和顺序设置的。

    Complex band-pass delta sigma AD modulator for use in AD converter circuit
    4.
    发明申请
    Complex band-pass delta sigma AD modulator for use in AD converter circuit 失效
    用于AD转换器电路的复合带通三角ΣAD调制器

    公开(公告)号：US20050285766A1

    公开(公告)日：2005-12-29

    申请号：US11157848

    申请日：2005-06-22

    申请人： Hao San ,  Haruo Kobayashi ,  Hiroki Wada ,  Atsushi Wada

    发明人： Hao San ,  Haruo Kobayashi ,  Hiroki Wada ,  Atsushi Wada

    IPC分类号： H03M1/06 ,  H03M3/00 ,  H03M3/04

    CPC分类号： H03M3/34 ,  H03M1/0665 ,  H03M3/40 ,  H03M3/424 ,  H03M3/464

    摘要： A complex band-pass ΔΣ AD modulator is provided with a subtracter device, a complex band-pass filter, first and second AD converters, and first and second DA converters. The first and second DA converters and first and second logic circuits are sandwiched by first and second multiplexers. At a first timing of a clock signal, the first multiplexer inputs and outputs the first and second digital signals as they are, and at a second timing thereof, the first multiplexer inputs the first and second digital signals, and outputs the first digital signal as a second digital signal and outputs the second digital signal as a first digital signal. The second multiplexer inputs and outputs first and second analog signals similarly. The first and second logic circuits substantially noise-shapes non-linearities of the first and second DA converters by realizing complex digital and analog filters, using high-pass and low-pass element rotation methods.

    摘要翻译： 复数带通DeltaSigma AD调制器具有减法器件，复带通滤波器，第一和第二AD转换器以及第一和第二DA转换器。 第一和第二DA转换器和第一和第二逻辑电路夹在第一和第二多路复用器之间。 在时钟信号的第一定时，第一多路复用器原样输入并输出第一和第二数字信号，并且在其第二定时，第一多路复用器输入第一和第二数字信号，并将第一数字信号作为 第二数字信号并输出​​第二数字信号作为第一数字信号。 第二多路复用器类似地输入和输出第一和第二模拟信号。 通过使用高通和低通元素旋转方法实现复杂的数字和模拟滤波器，第一和第二逻辑电路基本上噪声地形成第一和第二DA转换器的非线性。

    Analog-digital converter and method for converting analog signal into digital signal
    5.
    发明授权
    Analog-digital converter and method for converting analog signal into digital signal 有权
    模拟数字转换器和将模拟信号转换为数字信号的方法

    公开(公告)号：US08994572B2

    公开(公告)日：2015-03-31

    申请号：US14346260

    申请日：2012-09-06

    申请人： Hao San ,  Tsubasa Maruyama ,  Masao Hotta

    发明人： Hao San ,  Tsubasa Maruyama ,  Masao Hotta

    IPC分类号： H03M1/34 ,  H03M1/14 ,  H03M1/06 ,  H03M1/12 ,  H03M1/40

    CPC分类号： H03M1/14 ,  H03M1/0609 ,  H03M1/0692 ,  H03M1/0695 ,  H03M1/1014 ,  H03M1/1205 ,  H03M1/40 ,  H03M1/403 ,  H03M1/442

    摘要： The objective of the invention is to provide an A/D converter that exhibits fewer malfunctions due to variations in manufacturing. An A/D converter (1) of the invention, which is a cyclic type of analog/digital converter for converting an analog input signal to a digital signal having a predetermined resolution, comprises: a digital approximation unit (10) that includes a comparing unit (13) for comparing the magnitude of an input first analog signal with a threshold value to output a digital value indicating a result of the comparison and that also includes an MDAC unit (14) for amplifying the first analog signal to β-fold, where β is greater than one but smaller than two, and for executing a predetermined computation in accordance with the result of the comparison of the comparing unit to output a second analog signal; a multiplexer (20) that, if the MSB is to be computed, outputs the analog input signal and, otherwise, outputs the second analog signal as the first analog signal; a β estimating unit (30) that estimates the value of β; and a digital signal outputting unit (40) that sequentially takes in digital values outputted by the comparing unit and that outputs the taken-in digital values as the digital signal.

    摘要翻译： 本发明的目的是提供一种A / D转换器，其由于制造变化而表现出较少的故障。 本发明的A / D转换器（1）是用于将模拟输入信号转换为具有预定分辨率的数字信号的循环型模拟/数字转换器，包括：数字近似单元（10），包括比较 单元（13），用于将输入的第一模拟信号的幅度与阈值进行比较，以输出指示比较结果的数字值，并且还包括用于将第一模拟信号放大到＆bgr;折叠的MDAC单元（14） ，其中＆bgr 大于1但小于2，并且用于根据比较单元的比较结果执行预定的计算以输出第二模拟信号; 多路复用器（20），如果要计算MSB，则输出模拟输入信号，否则输出第二模拟信号作为第一模拟信号; 一个 估计单位（30）估计值 以及数字信号输出单元（40），其顺序地取入由比较单元输出的数字值，并将所接收的数字值作为数字信号输出。

    ANALOG/DIGITAL CONVERTER AND METHOD FOR CONVERTING ANALOG SIGNALS TO DIGITAL SIGNALS
    6.
    发明申请
    ANALOG/DIGITAL CONVERTER AND METHOD FOR CONVERTING ANALOG SIGNALS TO DIGITAL SIGNALS 有权
    用于将模拟信号转换为数字信号的模拟/数字转换器和方法

    公开(公告)号：US20140300500A1

    公开(公告)日：2014-10-09

    申请号：US14346260

    申请日：2012-09-06

    申请人： Hao San ,  Tsubasa Maruyama ,  Masao Hotta

    发明人： Hao San ,  Tsubasa Maruyama ,  Masao Hotta

    IPC分类号： H03M1/14 ,  H03M1/12

    CPC分类号： H03M1/14 ,  H03M1/0609 ,  H03M1/0692 ,  H03M1/0695 ,  H03M1/1014 ,  H03M1/1205 ,  H03M1/40 ,  H03M1/403 ,  H03M1/442

    摘要： The objective of the invention is to provide an A/D converter that exhibits fewer malfunctions due to variations in manufacturing. An A/D converter (1) of the invention, which is a cyclic type of analog/digital converter for converting an analog input signal to a digital signal having a predetermined resolution, comprises: a digital approximation unit (10) that includes a comparing unit (13) for comparing the magnitude of an input first analog signal with a threshold value to output a digital value indicating a result of the comparison and that also includes an MDAC unit (14) for amplifying the first analog signal to β-fold, where β is greater than one but smaller than two, and for executing a predetermined computation in accordance with the result of the comparison of the comparing unit to output a second analog signal; a multiplexer (20) that, if the MSB is to be computed, outputs the analog input signal and, otherwise, outputs the second analog signal as the first analog signal; a β estimating unit (30) that estimates the value of β; and a digital signal outputting unit (40) that sequentially takes in digital values outputted by the comparing unit and that outputs the taken-in digital values as the digital signal.

    摘要翻译： 本发明的目的是提供一种A / D转换器，其由于制造变化而表现出较少的故障。 本发明的A / D转换器（1）是用于将模拟输入信号转换为具有预定分辨率的数字信号的循环型模拟/数字转换器，包括：数字近似单元（10），包括比较 单元（13），用于将输入的第一模拟信号的幅度与阈值进行比较，以输出指示比较结果的数字值，并且还包括用于将第一模拟信号放大到＆bgr;折叠的MDAC单元（14） ，其中＆bgr 大于1但小于2，并且用于根据比较单元的比较结果执行预定的计算以输出第二模拟信号; 多路复用器（20），如果要计算MSB，则输出模拟输入信号，否则输出第二模拟信号作为第一模拟信号; 一个 估计单位（30）估计值 以及数字信号输出单元（40），其顺序地取入由比较单元输出的数字值，并将所接收的数字值作为数字信号输出。

    High-Precision Multi-Band Pass Delta-Sigma Modulator
    7.
    发明申请
    High-Precision Multi-Band Pass Delta-Sigma Modulator 失效
    高精度多通道Delta-Sigma调制器

    公开(公告)号：US20090167581A1

    公开(公告)日：2009-07-02

    申请号：US12096021

    申请日：2006-08-01

    申请人： Hiroyuki Hagiwara ,  Atsushi Motozawa ,  Haruo Kobayashi ,  Hao San

    发明人： Hiroyuki Hagiwara ,  Atsushi Motozawa ,  Haruo Kobayashi ,  Hao San

    IPC分类号： H03M3/00

    CPC分类号： H03M1/0665 ,  H03M1/74 ,  H03M3/338 ,  H03M3/424 ,  H03M3/464

    摘要： A high-precision ΔΣ modulator reduces nonlinear noise due to the use of a multibit DAC and has little hardware and power consumption. A digital signal is DA converted and fed back to a subtraction circuit supplied with an analog signal. The DAC used in this feedback circuit uses a DAC (DWADAC) that includes a weighted pointer so that input digital signals are supplied in order to a plurality of segment elements that construct the DAC. In this DWADAC, the construction and number of the pointer is set based on the type and order of the filter disposed before the ADC.

    摘要翻译： 高精度DeltaSigma调制器由于使用多位DAC而降低了非线性噪声，几乎没有硬件和功耗。 数字信号被DA转换并反馈到提供有模拟信号的减法电路。 在该反馈电路中使用的DAC使用包括加权指针的DAC（DWADAC），以便为构成DAC的多个段元件提供输入数字信号。 在这个DWADAC中，指针的构造和数量是根据ADC之前设置的滤波器的类型和顺序设置的。

    DA converter circuit provided with DA converter of segment switched capacitor type
    9.
    发明申请
    DA converter circuit provided with DA converter of segment switched capacitor type 失效
    DA转换电路配有片段开关电容型DA转换器

    公开(公告)号：US20050285768A1

    公开(公告)日：2005-12-29

    申请号：US11157923

    申请日：2005-06-22

    申请人： Hiroyuki Hagiwara ,  Haruo Kobayashi ,  Hao San ,  Atsushi Wada

    发明人： Hiroyuki Hagiwara ,  Haruo Kobayashi ,  Hao San ,  Atsushi Wada

    IPC分类号： H03M1/06 ,  H03M1/66 ,  H03M1/80 ,  H03M3/00 ,  H03M3/04

    CPC分类号： H03M1/0665 ,  H03M1/806 ,  H03M3/43 ,  H03M3/464

    摘要： A DA converter circuit is provided for use in a ΔΣ AD modulator. The DA converter circuit includes a DA converter of segment switched capacitor type. The DA converter includes an operational amplifier, capacitors as connected in parallel to each other to supply electric charges to the operational amplifier, an electrically charging switch for switching of electrically charging electric charges onto the respective capacitors or not, and an electrically discharging switch for switching or not electrically discharging electric charges from the respective capacitors or not. A switch device performs either one of the electrically charging, the electrically discharging, grounding, and polarity inversion onto the respective capacitors. A controller controls the electrically charging switch, the electrically discharging switch and the switch device to execute a process of second-order DWA algorithm for performing a second-order noise shaping of a non-linearity of the DA converter circuit.

    摘要翻译： 提供了用于DeltaSigma AD调制器的DA转换器电路。 DA转换器电路包括段转换电容器类型的DA转换器。 DA转换器包括运算放大器，彼此并联连接的电容器，以向运算放大器提供电荷，用于将充电电荷转换到各个电容器上的充电开关，以及用于切换的放电开关 或不从各个电容器中电荷放电。 开关装置对各个电容器进行充电，放电，接地和极性反转之一。 控制器控制充电开关，放电开关和开关装置，以执行用于执行DA转换器电路的非线性的二阶噪声整形的二阶DWA算法的处理。

    Complex bandpass ΔΣAD modulator and digital radio receiver
    10.
    发明授权
    Complex bandpass ΔΣAD modulator and digital radio receiver 有权
    复数带通DeltaSigmaAD调制器和数字无线电接收器

    公开(公告)号：US08436757B2

    公开(公告)日：2013-05-07

    申请号：US13254333

    申请日：2010-02-24

    申请人： Hao San ,  Haruo Kobayashi

    发明人： Hao San ,  Haruo Kobayashi

    IPC分类号： H03M3/00

    CPC分类号： H03M3/368 ,  H03M3/40

    摘要： To provide a complex bandpass ΔΣAD modulator capable of suppressing the influence of an image component caused by a mismatch between I- and Q-channels on a signal component with low power consumption.A complex bandpass ΔΣAD modulator 10 is configured by a subtraction unit 20, a complex bandpass filter 30, an addition unit 40, a noise extraction circuit unit 50, an ADC unit 60, and a DAC unit 70. The noise extraction circuit unit 50 extracts a quantized noise signal of the ADC unit 60 based on an input signal of the ADC unit 60 and an output signal of the DAC unit 70, delays the extracted quantized noise signal by one sample time, phase-rotates the delayed signal by a predetermined angle, and feeds back the rotated signal to the input side of the ADC unit 60. Thus, a complex bandpass ΔΣAD modulator capable of suppressing the influence of the image component caused by a mismatch between I- and Q-channels on the signal component with low power consumption is provided.

    摘要翻译： 提供一种复杂的带通DeltaSigmaAD调制器，其能够抑制由I信道和Q信道之间的失配引起的图像分量对具有低功耗的信号分量的影响。 复数带通DeltaSigmaAD调制器10由减法单元20，复带通滤波器30，加法单元40，噪声提取电路单元50，ADC单元60和DAC单元70构成。噪声提取电路单元50提取 基于ADC单元60的输入信号和DAC单元70的输出信号的ADC单元60的量化噪声信号将所提取的量化噪声信号延迟一个采样时间，将延迟信号相位旋转预定角度 ，并将旋转的信号反馈到ADC单元60的输入侧。因此，能够抑制由I信道和Q信道之间的失配引起的图像分量对信号分量的影响的复数带通DeltaSigmaAD调制器 提供功耗。