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    Lithography process to reduce interference
    2.
    发明申请
    Lithography process to reduce interference 审中-公开
    光刻过程减少干扰

    公开(公告)号：US20070087291A1

    公开(公告)日：2007-04-19

    申请号：US11252499

    申请日：2005-10-18

    申请人： Tsai-Sheng Gau ,  Jaw-Jung Shin ,  Chun-Kuang Chen ,  Jan-Wen You ,  Burn-Jeng Lin

    发明人： Tsai-Sheng Gau ,  Jaw-Jung Shin ,  Chun-Kuang Chen ,  Jan-Wen You ,  Burn-Jeng Lin

    IPC分类号： G03F7/20

    CPC分类号： G03F7/70466 ,  G03F1/70 ,  G03F7/203 ,  G03F7/70425

    摘要： A method and associated masks for carrying out a lithographic imaging process to reduce or avoid a strong interference effect in off-axis illumination, the method including providing a resist layer on a substrate; illuminating a first group of line patterns through a first mask on the resist layer; illuminating a second group of line patterns through a second mask on the resist layer, the second group of line patterns oriented nonparallel with respect to the first group of line patterns; and, developing the illuminated resist layer.

    摘要翻译： 一种用于进行光刻成像处理以减少或避免在离轴照明中的强干涉效应的方法和相关掩模，所述方法包括在基板上提供抗蚀剂层; 通过抗蚀剂层上的第一掩模照射第一组线图案; 通过抗蚀剂层上的第二掩模照射第二组线图案，第二组线条图案相对于第一组线图案取向不平行; 并且显影照射的抗蚀剂层。

    Method of defining forbidden pitches for a lithography exposure tool
    3.
    发明授权
    Method of defining forbidden pitches for a lithography exposure tool 失效
    定义光刻曝光工具的禁止间距的方法

    公开(公告)号：US06973636B2

    公开(公告)日：2005-12-06

    申请号：US10688500

    申请日：2003-10-17

    申请人： Jaw-Jung Shin ,  Chun-Kuang Chen ,  Tsai-Sheng Gau ,  Burn-Jeng Lin ,  Li-Chun Tien ,  Mi-Chang Chang ,  Yu-Jun Chou ,  Jan-Wen You ,  King-Chang Shu ,  Li-Jui Chen

    发明人： Jaw-Jung Shin ,  Chun-Kuang Chen ,  Tsai-Sheng Gau ,  Burn-Jeng Lin ,  Li-Chun Tien ,  Mi-Chang Chang ,  Yu-Jun Chou ,  Jan-Wen You ,  King-Chang Shu ,  Li-Jui Chen

    IPC分类号： G03F1/14 ,  G03F7/20 ,  G06F17/50

    CPC分类号： G03F7/70641 ,  G03F1/44 ,  G03F7/70425 ,  G03F7/70433 ,  G03F7/705

    摘要： A method of identifying and defining forbidden pitches or forbidden pitch ranges for a lithographic exposure tool under a given set of exposure conditions is provided. In the method, a computer simulation is performed, and its results are compared to frequently used pitches to see if such frequently used pitches may yield depth-of-focus (DOF) values greater than the focus budget for the exposure tool. If so, a verification test is performed by using a test mask and actually exposing a surface with the same pattern pitches simulated. From this, actual DOF values are obtained and compared to the focus budget of the exposure tool. Any pitches having a DOF value greater than the focus budget are designated as forbidden pitches. This forbidden pitch information may be integrated into a design rule to restrict the use of such forbidden pitches under the given exposure conditions where they are likely to arise.

    摘要翻译： 提供了一种在给定的曝光条件下识别和限定光刻曝光工具的禁止间距或禁止间距范围的方法。 在该方法中，执行计算机模拟，并将其结果与经常使用的间距进行比较，以查看这种经常使用的间距是否可以产生比曝光工具的焦点预算大的焦点深度（DOF）值。 如果是这样，则通过使用测试掩模执行验证测试，并且实际上暴露出模拟相同模式间距的表面。 从此，获得实际的DOF值，并与曝光工具的焦点预算进行比较。 DOF值大于焦点预算的任何间距都被指定为禁止间距。 该禁止音调信息可以被集成到设计规则中，以限制在可能出现的给定曝光条件下使用这种禁止间距。

    Method for improving the critical dimension uniformity of patterned features on wafers
    4.
    发明授权
    Method for improving the critical dimension uniformity of patterned features on wafers 有权
    改善晶片上图形特征的临界尺寸均匀性的方法

    公开(公告)号：US07234128B2

    公开(公告)日：2007-06-19

    申请号：US10678788

    申请日：2003-10-03

    申请人： Tsai-Sheng Gau ,  Jaw-Jung Shin ,  Jan-Wen You ,  Burn-Jeng Lin

    发明人： Tsai-Sheng Gau ,  Jaw-Jung Shin ,  Jan-Wen You ,  Burn-Jeng Lin

    IPC分类号： G06F17/50 ,  G06F19/00 ,  G06K9/00

    CPC分类号： G03F7/70616 ,  G03F7/70441 ,  G06T7/0004 ,  G06T2207/30148

    摘要： A method for improving the critical dimension uniformity of a patterned feature on a wafer in semiconductor and mask fabrication is provided. In one embodiment, an evaluation means for evaluating the critical dimension distribution of a plurality of circuit layouts formed on the wafer, the plurality of circuit layouts defined by a mask is provided. A logic operation is performed on the plurality of circuit layouts to extract the patterned feature. The patterned feature is compared with design rules and if there is a deviation or difference between the patterned feature and the design rules, this difference is compensated for by adjusting photolithography adjustable parameters, such as, for example, mask-making.

    摘要翻译： 提供了一种用于改善半导体和掩模制造中的晶片上的图案化特征的临界尺寸均匀性的方法。 在一个实施例中，提供了一种用于评估形成在晶片上的多个电路布局的临界尺寸分布的评估装置，提供了由掩模限定的多个电路布局。 对多个电路布局执行逻辑操作以提取图案化特征。 将图案特征与设计规则进行比较，并且如果图案特征和设计规则之间存在偏差或差异，则通过调整光刻可调参数（例如掩模制作）来补偿该差异。

    Method for improving the critical dimension uniformity of patterned features on wafers
    5.
    发明申请
    Method for improving the critical dimension uniformity of patterned features on wafers 有权
    改善晶片上图形特征的临界尺寸均匀性的方法

    公开(公告)号：US20050076323A1

    公开(公告)日：2005-04-07

    申请号：US10678788

    申请日：2003-10-03

    申请人： Tsai-Sheng Gau ,  Jaw-Jung Shin ,  Jan-Wen You ,  Burn-Jeng Lin

    发明人： Tsai-Sheng Gau ,  Jaw-Jung Shin ,  Jan-Wen You ,  Burn-Jeng Lin

    IPC分类号： G03F7/20 ,  G06T7/00 ,  G06F17/50 ,  G06K9/00

    CPC分类号： G03F7/70616 ,  G03F7/70441 ,  G06T7/0004 ,  G06T2207/30148

    摘要： A method for improving the critical dimension uniformity of a patterned feature on a wafer in semiconductor and mask fabrication is provided. In one embodiment, an evaluation means for evaluating the critical dimension distribution of a plurality of circuit layouts formed on the wafer, the plurality of circuit layouts defined by a mask is provided. A logic operation is performed on the plurality of circuit layouts to extract the patterned feature. The patterned feature is compared with design rules and if there is a deviation or difference between the patterned feature and the design rules, this difference is compensated for by adjusting photolithography adjustable parameters, such as, for example, mask-making.

    摘要翻译： 提供了一种用于改善半导体和掩模制造中的晶片上的图案化特征的临界尺寸均匀性的方法。 在一个实施例中，提供了一种用于评估形成在晶片上的多个电路布局的临界尺寸分布的评估装置，提供了由掩模限定的多个电路布局。 对多个电路布局执行逻辑操作以提取图案化特征。 将图案特征与设计规则进行比较，并且如果图案特征和设计规则之间存在偏差或差异，则通过调整光刻可调参数（例如掩模制作）来补偿该差异。

    Method and system for a pattern layout split
    6.
    发明授权
    Method and system for a pattern layout split 有权
    图案布局拆分的方法和系统

    公开(公告)号：US07934177B2

    公开(公告)日：2011-04-26

    申请号：US11671866

    申请日：2007-02-06

    申请人： Jaw-Jung Shin ,  King-Chang Shu ,  Tsai-Sheng Gau ,  Burn Jeng Lin

    发明人： Jaw-Jung Shin ,  King-Chang Shu ,  Tsai-Sheng Gau ,  Burn Jeng Lin

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G03F1/36 ,  G03F1/70 ,  G03F7/70466

    摘要： A method for splitting a pattern layout including providing the pattern layout having features, checking the pattern layout to determine the features that require splitting, coloring the features that require splitting with a first and second color, resolving coloring conflicts by decomposing the feature with the coloring conflict and coloring the decomposed feature with the first and second color, and generating a first mask with features of the first color and a second mask with features of the second color.

    摘要翻译： 一种用于分割图案布局的方法，包括提供具有特征的图案布局，检查图案布局以确定需要分割的特征，着色需要用第一和第二颜色分割的特征，通过用着色分解特征来解决着色冲突 冲突和着色具有第一和第二颜色的分解特征，以及生成具有第一颜色特征的第一掩模和具有第二颜色特征的第二掩模。

    Method and System For a Pattern Layout Split
    7.
    发明申请
    Method and System For a Pattern Layout Split 有权
    图案布局拆分的方法和系统

    公开(公告)号：US20080189672A1

    公开(公告)日：2008-08-07

    申请号：US11671866

    申请日：2007-02-06

    申请人： Jaw-Jung Shin ,  King-Chang Shu ,  Tsai-Sheng Gau ,  Burn Jeng Lin

    发明人： Jaw-Jung Shin ,  King-Chang Shu ,  Tsai-Sheng Gau ,  Burn Jeng Lin

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068 ,  G03F1/36 ,  G03F1/70 ,  G03F7/70466

    摘要： A method for splitting a pattern layout including providing the pattern layout having features, checking the pattern layout to determine the features that require splitting, coloring the features that require splitting with a first and second color, resolving coloring conflicts by decomposing the feature with the coloring conflict and coloring the decomposed feature with the first and second color, and generating a first mask with features of the first color and a second mask with features of the second color.

    摘要翻译： 一种用于分割图案布局的方法，包括提供具有特征的图案布局，检查图案布局以确定需要分割的特征，着色需要用第一和第二颜色分割的特征，通过用着色分解特征来解决着色冲突 冲突和着色具有第一和第二颜色的分解特征，以及生成具有第一颜色特征的第一掩模和具有第二颜色特征的第二掩模。

    Method and system for identifying lens aberration sensitive patterns in an integrated circuit chip
    8.
    发明授权
    Method and system for identifying lens aberration sensitive patterns in an integrated circuit chip 失效
    用于识别集成电路芯片中的透镜像差敏感图案的方法和系统

    公开(公告)号：US07643976B2

    公开(公告)日：2010-01-05

    申请号：US11421618

    申请日：2006-06-01

    申请人： Jaw-Jung Shin ,  King-Chang Shu ,  Jan-Wen You ,  Tsai-Sheng Gau

    发明人： Jaw-Jung Shin ,  King-Chang Shu ,  Jan-Wen You ,  Tsai-Sheng Gau

    IPC分类号： G06F9/455

    CPC分类号： G03F7/70433 ,  G03F7/705 ,  G03F7/706

    摘要： Disclosed is a method and a system for identifying lens aberration sensitive patterns in an integrated circuit chip. A first simulation of a layout is performed to simulate a contour without lens aberration. A second simulation is performed of the layout to simulate a contour with lens aberration. A difference of critical dimension is determined between the contours with and without lens aberration, and at least one lens aberration sensitive pattern is selected from a plurality of layouts based on the difference in critical dimension.

    摘要翻译： 公开了用于识别集成电路芯片中的透镜像差敏感图案的方法和系统。 执行布局的第一模拟以模拟没有透镜像差的轮廓。 执行布局以模拟具有透镜像差的轮廓的第二模拟。 在具有和不具有透镜像差的轮廓之间确定临界尺寸的差异，并且基于临界尺寸的差异从多个布局中选择至少一个透镜像差敏感图案。

    Immersion optical projection system
    10.
    发明申请
    Immersion optical projection system 有权
    浸入式光学投影系统

    公开(公告)号：US20050286030A1

    公开(公告)日：2005-12-29

    申请号：US11009505

    申请日：2004-12-10

    申请人： Jen-Chieh Shih ,  Burn-Jeng Lin ,  Tsai-Sheng Gau ,  Ru-Gun Liu ,  Chun-Kuang Chen ,  Chin-Hsiang Lin ,  Horng-Huei Tseng

    发明人： Jen-Chieh Shih ,  Burn-Jeng Lin ,  Tsai-Sheng Gau ,  Ru-Gun Liu ,  Chun-Kuang Chen ,  Chin-Hsiang Lin ,  Horng-Huei Tseng

    IPC分类号： G03B27/52 ,  G03F7/20

    CPC分类号： G03F7/70341

    摘要： An immersion optical projection system for photolithography is provided. A transparent plate is located between a last lens element and the wafer during a usage of the system. The transparent plate has a lens-side surface and a wafer-side surface. The system is adapted to have a layer of lens-side fluid located between the last lens element and the lens-side surface of the transparent plate, e.g., when the last lens element is operably located over the wafer during a photolithography process. The system is also adapted to have a layer of wafer-side fluid located between the wafer-side surface of the transparent plate and the wafer, during a usage of the system. The wafer-side fluid may or may not be fluidly connected to the lens-side fluid. The wafer-side fluid may or may not differ from the lens-side fluid.

    摘要翻译： 提供了一种用于光刻的浸没式光学投影系统。 在使用系统期间，透明板位于最后一个透镜元件和晶片之间。 透明板具有透镜侧表面和晶片侧表面。 该系统适于具有位于最后透镜元件和透明板的透镜侧表面之间的透镜侧流体层，例如当光刻工艺期间最后一个透镜元件可操作地位于晶片上方时。 该系统还适于在系统的使用期间具有位于透明板的晶片侧表面和晶片之间的晶片侧流体层。 晶片侧流体可以或可以不流体地连接到透镜侧流体。 晶片侧流体可以或可以不与透镜侧流体不同。