公开(公告)号：US4542398A

公开(公告)日：1985-09-17

申请号：US621370

申请日：1984-06-18

申请人： Tsutomu Yatsuo ,  Masayoshi Naito ,  Takahiro Nagano ,  Tomio Yasuda ,  Jin Onuki ,  Mitsuo Yanagi ,  Fumio Sato

发明人： Tsutomu Yatsuo ,  Masayoshi Naito ,  Takahiro Nagano ,  Tomio Yasuda ,  Jin Onuki ,  Mitsuo Yanagi ,  Fumio Sato

IPC分类号： H01L29/74 ,  H01L21/52 ,  H01L23/48 ,  H01L23/482 ,  H01L29/08 ,  H01L29/423 ,  H01L29/744

CPC分类号： H01L23/4824 ,  H01L24/72 ,  H01L29/0804 ,  H01L29/42304 ,  H01L29/42308 ,  H01L29/744 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/1301 ,  H01L2924/19043

摘要： A multi-emitter type semiconductor device, namely, a semiconductor device having an arrangement in which a majority of emitter regions are divided by a gate region and surrounded thereby. In the semiconductor device, a member adapted to apply an external control signal to a gate electrode takes the form of a closed-loop shape and the majority of emitter regions are arranged on both sides of the loop. This arrangement ensures that the individual emitter regions, even when the number of the emitter regions is increased to a great extent, can be applied with a uniform control signal, thereby preventing degradation of the turn-off characteristics.

摘要翻译： 多射极型半导体器件，即具有这样一种布置的半导体器件，其中大部分发射极区域被栅极区域分开并被其包围。 在半导体器件中，适于向栅电极施加外部控制信号的部件采取闭环形状，并且大部分发射极区域布置在环路的两侧。 这种布置确保即使当发射极区域的数量增加到很大程度时，各个发射极区域也可以应用均匀的控制信号，从而防止关断特性的劣化。

公开(公告)号：US4626888A

公开(公告)日：1986-12-02

申请号：US550586

申请日：1983-11-10

申请人： Takahiro Nagano ,  Tsutomu Yatsuo ,  Saburo Oikawa ,  Akira Horie

发明人： Takahiro Nagano ,  Tsutomu Yatsuo ,  Saburo Oikawa ,  Akira Horie

IPC分类号： H01L29/423 ,  H01L29/74 ,  H01L29/744 ,  H01L23/48

CPC分类号： H01L29/42308 ,  H01L29/74 ,  H01L29/744

摘要： In accordance with the present invention, a plurality of strip-shaped emitter layers on the cathode side are radially arranged on one main surface of the semiconductor substrate while forming a plurality of rings. A gate electrode is in ohmic contact with a part of a base layer which surrounds and is adjacent to each of said emitter layers on the cathode side. Between rings formed by said emitter layers on the cathode side, a ring-shaped gate collecting electrode is provided to be connected to said gate electrode. The gate collecting electrode is provided at a position to balance the potential differences produced by gate currents respectively corresponding to inside and outside of said gate collecting electrode.

摘要翻译： 根据本发明，阴极侧的多个条状发射极层径向地布置在半导体衬底的一个主表面上，同时形成多个环。 栅电极与基极层的一部分欧姆接触，该基极层围绕并邻近阴极侧的每个发射极层。 在由阴极侧上的发射极层形成的环之间，设置有环形栅极集电极，以连接到所述栅电极。 栅极集电极设置在平衡由分别对应于所述栅极集电极的内部和外部的栅极电流产生的电位差的位置。

公开(公告)号：US4443810A

公开(公告)日：1984-04-17

申请号：US320536

申请日：1981-11-12

申请人： Tsutomu Yatsuo ,  Takahiro Nagano

发明人： Tsutomu Yatsuo ,  Takahiro Nagano

IPC分类号： H01L29/74 ,  H01L29/744

CPC分类号： H01L29/744

摘要： A gate turn-off thyristor is disclosed which includes a main thyristor having a shorted emitter structure on the anode side thereof and an auxiliary thyristor having a shorted emitter structure on the cathode side thereof and wherein the cathode of the auxiliary thyristor is connected to the gate of the main thyristor to on-off control a large current by a small gate signal.

摘要翻译： 公开了一种栅极截止晶闸管，其包括在其阳极侧具有短路发射极结构的主晶闸管和在其阴极侧具有短路发射极结构的辅助晶闸管，并且其中辅助晶闸管的阴极连接到栅极 的主晶闸管开关通过小门信号控制大电流。

公开(公告)号：US4651189A

公开(公告)日：1987-03-17

申请号：US680837

申请日：1984-12-12

申请人： Tsutomu Yatsuo ,  Takahiro Nagano ,  Saburo Oikawa ,  Yukimasa Sato ,  Shin Kimura ,  Hiroshi Fukui

发明人： Tsutomu Yatsuo ,  Takahiro Nagano ,  Saburo Oikawa ,  Yukimasa Sato ,  Shin Kimura ,  Hiroshi Fukui

IPC分类号： H01L29/08 ,  H01L29/10 ,  H01L29/167 ,  H01L29/32 ,  H01L29/423 ,  H01L29/744 ,  H01L29/74

CPC分类号： H01L29/744 ,  H01L29/0804 ,  H01L29/0834 ,  H01L29/0839 ,  H01L29/1004 ,  H01L29/102 ,  H01L29/167 ,  H01L29/32 ,  H01L29/42304 ,  H01L29/42308

摘要： A gate turn-off thyristor and a transistor are disclosed, each of which comprises: a semiconductor substrate including at least three semiconductor layers between a pair of principal surfaces, adjacent ones of the semiconductor layers being different in conductivity type from each other, a first one of the semiconductor layers being formed of at least one strip-shaped region with a constant width, a second one of the semiconductor layers being exposed to a first principal surface of the semiconductor substrate together with the strip-shaped region; a first main electrode kept in ohmic contact with the strip-shaped region at the first principal surface; a first control electrode kept in ohmic contact with the second semiconductor layer on one side of the strip-shaped region in the direction of the width thereof and connected directly to a control terminal; a second control electrode kept in ohmic contact with the second semiconductor layer on the other side of the strip-shaped region in the direction of the width thereof and connected to the control terminal through the first control electrode and the resistance of the second semiconductor layer between the first control electrode and the second control electrode; a second main electrode kept in ohmic contact with a second principal surface of the semiconductor substrate; and means provided in the semiconductor substrate for accelerating the spatial biasing of a conductive region to the other side of the strip-shaped region in the direction of the width thereof when a current flowing across the semiconductor substrate is cut off, thereby enlarging the area of safety operation.

摘要翻译： 公开了一种栅极截止晶闸管和晶体管，每个晶体管包括：半导体衬底，其在一对主表面之间包括至少三个半导体层，相邻的半导体层之间的导电类型彼此不同，第一 一个半导体层由至少一个具有恒定宽度的条形区域形成，第二个半导体层与条形区域一起暴露于半导体衬底的第一主表面; 第一主电极与第一主表面处的带状区域欧姆接触; 第一控制电极在带状区域的宽度方向上与第二半导体层保持欧姆接触，并直接连接到控制端子; 第二控制电极在带状区域的另一侧沿其宽度方向与第二半导体层欧姆接触，并且通过第一控制电极连接到控制端子，并且第二控制电极与第二半导体层之间的电阻 所述第一控制电极和所述第二控制电极; 与所述半导体衬底的第二主表面保持欧姆接触的第二主电极; 以及设置在半导体衬底中的装置，用于当切断流过半导体衬底的电流时，在导电区域的宽度方向上将导电区域的空间偏置加速到带状区域的另一侧，从而扩大 安全运行。

公开(公告)号：US4646122A

公开(公告)日：1987-02-24

申请号：US585606

申请日：1984-03-02

申请人： Shin Kimura ,  Hiroshi Fukui ,  Hisao Amano ,  Tsutomu Yatsuo ,  Saburo Oikawa ,  Takahiro Nagano

发明人： Shin Kimura ,  Hiroshi Fukui ,  Hisao Amano ,  Tsutomu Yatsuo ,  Saburo Oikawa ,  Takahiro Nagano

IPC分类号： H01L29/423 ,  H01L29/74

CPC分类号： H01L29/42304 ,  H01L29/42308

摘要： A semiconductor device such as a transistor or gate turn-off thyristor provided with a control electrode for improving the current cut-off performance, is disclosed in which an emitter layer of a semiconductor substrate is formed of a plurality of strip-shaped regions, a base layer adjacent to the strip-shaped regions is exposed to one principal surface of the semiconductor substrate together with the strip-shaped regions, one main electrode is provided on each strip-shaped region, first and second control electrodes are provided on the base layer, on one and the other sides of each strip-shaped region viewed in the direction of the width thereof, respectively, the other main electrode is provided on the second principal surface of the semiconductor substrate, and a gate terminal is not connected to the first control electrode but connected to the second control electrode, in order to draw out carriers unequally by the first and second control electrodes at a turn-off period. At the initial stage of turn-off action, carriers are drawn out mainly by the second control terminal, and a conductive region contracts so as to be limited to the first control electrode side. At the final stage of turn-off action, carriers are drawn out considerably by the first control electrode, to complete the turn-off action.

摘要翻译： 公开了一种半导体器件，例如晶体管或栅极截止晶闸管，其设置有用于提高电流截止性能的控制电极，其中半导体衬底的发射极层由多个条形区域形成， 与带状区域相邻的基底层与条状区域一起暴露于半导体衬底的一个主表面，在每个条形区域上设置一个主电极，在基底层上设置第一和第二控制电极 在从宽度方向观察的每个条形区域的一侧和另一侧上分别设置在该半导体衬底的第二主表面上，另一个主电极没有连接到第一 控制电极，但是连接到第二控制电极，以便在关断周期期间由第一和第二控制电极不相等地引出载流子。 在关断动作的初始阶段，主要由第二控制端子引出载体，并且导电区域收缩以限于第一控制电极侧。 在关断动作的最后阶段，载体被第一控制电极显着地拉出，以完成关断动作。

公开(公告)号：US4500903A

公开(公告)日：1985-02-19

申请号：US384520

申请日：1982-06-03

申请人： Tsutomu Yatsuo ,  Takahiro Nagano ,  Saburo Oikawa ,  Akira Horie

发明人： Tsutomu Yatsuo ,  Takahiro Nagano ,  Saburo Oikawa ,  Akira Horie

IPC分类号： H01L29/08 ,  H01L29/74 ,  H01L29/744

CPC分类号： H01L29/0839 ,  H01L29/74 ,  H01L29/744

摘要： A gate turn-off thyristor in which a cathode-emitter layer is divided into a plurality of strip-like regions which are radially arrayed on a major surface of a semiconductor substrate in a coaxial multi-ring pattern including a plurality of coaxially arrayed rings. The cathode-emitter strips belonging to a given one of the rings have some radial length. The cathode-emitter strips belonging to the inner ring of a coaxial multi-ring pattern have a smaller radial length than that of the cathode-emitter strips constituting the outer ring. A cathode electrode is contacted to the cathode-emitter strip in low resistance ohmic contact. A gate electrode is ohmic contacted with a low resistance to a cathode-base layer located adjacent to the cathode-emitter strip so as to enclose it. An anode electrode is ohmic contacted with a low resistance to the anode-emitter layer. With the structure of GTO, turn-off operation of unit GTO's each including a cathode-emitter strip is equalized.

摘要翻译： 一种栅极截止晶闸管，其中阴极 - 发射极层被分成多个条形区域，其以包括多个同轴排列的环的同轴多环图案在半导体衬底的主表面上径向排列。 属于给定一个环的阴极 - 发射极条具有一些径向长度。 属于同轴多环形图案的内环的阴极发射极条的径向长度小于构成外环的阴极 - 发射极条的长度。 阴极电极以低电阻欧姆接触与阴极 - 发射极条接触。 栅电极与位于阴极 - 发射极条附近的阴极 - 基底层的低电阻欧姆接触，以便包围它。 阳极电极与对阳极 - 发射极层的低电阻欧姆接触。 利用GTO的结构，使包括阴极 - 发射极条的单元GTO的关断操作相等。

公开(公告)号：US08835933B2

公开(公告)日：2014-09-16

申请号：US13392786

申请日：2010-08-27

申请人： Takahiro Nagano ,  Mitsuo Okamoto ,  Tsutomu Yatsuo ,  Kenji Fukuda

发明人： Takahiro Nagano ,  Mitsuo Okamoto ,  Tsutomu Yatsuo ,  Kenji Fukuda

IPC分类号： H01L29/15 ,  H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L29/16

CPC分类号： H01L29/7834 ,  H01L29/1608 ,  H01L29/66068

摘要： A SiC MISFET, in which a source region and a drain region (3, 4) are formed in a one-conductivity-type SiC semiconductor region (2), in which a recess (5) with a predetermined depth is formed in a portion of the SiC semiconductor region sandwiched between the source and drain regions, with the recess having two side faces in contact with the source and drain regions, and a bottom face connecting the two side faces, and in which portions (3a, 4a) of the source and drain regions adjacent to the vicinity of both ends of the bottom face of the recess are thinner than other portions.

摘要翻译： 在一导电型SiC半导体区域（2）中形成有源极区和漏极区（3,4）的SiC MISFET，其中形成具有预定深度的凹部（5） 夹在所述源极和漏极区之间的所述SiC半导体区域，其中所述凹部具有与所述源极和漏极区域接触的两个侧面，以及连接所述两个侧面的底面，并且其中所述凹部的所述部分（3a，4a） 与凹部的底面的两端附近相邻的源极和漏极区域比其它部分薄。

公开(公告)号：US20120153302A1

公开(公告)日：2012-06-21

申请号：US13392786

申请日：2010-08-27

申请人： Takahiro Nagano ,  Mitsuo Okamoto ,  Tsutomu Yatsuo ,  Kenji Fukuda

发明人： Takahiro Nagano ,  Mitsuo Okamoto ,  Tsutomu Yatsuo ,  Kenji Fukuda

IPC分类号： H01L29/161 ,  H01L21/336

CPC分类号： H01L29/7834 ,  H01L29/1608 ,  H01L29/66068

摘要： A SiC MISFET, in which a source region and a drain region (3, 4) are formed in a one-conductivity-type SiC semiconductor region (2), in which a recess (5) with a predetermined depth is formed in a portion of the SiC semiconductor region sandwiched between the source and drain regions, with the recess having two side faces in contact with the source and drain regions, and a bottom face connecting the two side faces, and in which portions (3a, 4a) of the source and drain regions adjacent to the vicinity of both ends of the bottom face of the recess are thinner than other portions.

摘要翻译： 在一导电型SiC半导体区域（2）中形成有源极区和漏极区（3,4）的SiC MISFET，其中形成具有预定深度的凹部（5） 夹在所述源极和漏极区之间的所述SiC半导体区域，其中所述凹部具有与所述源极和漏极区域接触的两个侧面，以及连接所述两个侧面的底面，并且其中所述凹部的所述部分（3a，4a） 与凹部的底面的两端附近相邻的源极和漏极区域比其它部分薄。

公开(公告)号：US4219832A

公开(公告)日：1980-08-26

申请号：US716280

申请日：1976-08-20

申请人： Masayoshi Naito ,  Takahiro Nagano ,  Takuzo Ogawa

发明人： Masayoshi Naito ,  Takahiro Nagano ,  Takuzo Ogawa

IPC分类号： H01L29/74 ,  H01L21/225 ,  H01L21/285 ,  H01L21/331 ,  H01L29/06 ,  H01L29/08 ,  H01L29/73

CPC分类号： H01L29/0834 ,  H01L21/2257 ,  H01L21/28525 ,  H01L29/0839

摘要： A thyristor comprising a four-layer semiconductor substrate of PNPN structure in which the sum of the thicknesses in the layered direction of the intermediate P-type and N-type layers is less than 400.mu., and the amount of impurities per unit area of either one of the outer P-type and N-type layers is less than 3.times.10.sup.14 atoms/cm.sup.2.

摘要翻译： 一种晶闸管，包括PNPN结构的四层半导体衬底，其中中间P型和N型层的层叠方向的厚度之和小于400μm，并且每单位面积的杂质量 外部P型和N型层之一小于3×1014原子/ cm 2。

公开(公告)号：US08913822B2

公开(公告)日：2014-12-16

申请号：US13433606

申请日：2012-03-29

申请人： Yasuhiro Matsuda ,  Takahiro Nagano ,  Masashi Uchida

发明人： Yasuhiro Matsuda ,  Takahiro Nagano ,  Masashi Uchida

IPC分类号： G06K9/36 ,  G06K9/40 ,  G06T3/40

CPC分类号： G06T3/4053 ,  G06T2207/10016 ,  G06T2207/20081

摘要： There is provided an image processing apparatus including a model-based processing unit that executes model-based processing for converting resolution and converting an image on the basis of a camera model and a predetermined model having aligning, with respect to a high-resolution image output one frame before, and a prediction operation unit that performs a prediction operation on a pixel value of a high-resolution image to be output, on the basis of parameters stored in advance, an observed low-resolution image that is an input low-resolution image, and an image obtained by executing the model-based processing.

摘要翻译： 提供了一种图像处理装置，包括：基于模型的处理单元，其基于相机模型和相对于高分辨率图像输出对准的预定模型执行基于模型的处理，用于转换分辨率和转换图像 基于预先存储的参数，对作为输出的低分辨率图像的低分辨率图像进行预测运算的预测运算部， 图像和通过执行基于模型的处理获得的图像。