公开(公告)号：US07807558B2

公开(公告)日：2010-10-05

申请号：US11933732

申请日：2007-11-01

申请人： Tzu-Ching Tsai ,  Tse-Yao Huang ,  Yi-Nan Chen

发明人： Tzu-Ching Tsai ,  Tse-Yao Huang ,  Yi-Nan Chen

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/02063 ,  H01L21/02071 ,  H01L21/32137

摘要： A method of fabricating a semiconductor device is provided. The method of fabricating the semiconductor device comprises providing a substrate. Next, an insulating layer, a conductive layer and a silicide layer are formed on the substrate in sequence. Next, a hard masking layer is formed on the silicide layer exposing a portion of the silicide layer. A first etching step is performed to remove the silicide layer and the underlying conductive layer which are not covered by the hard masking layer, thereby forming a gate stack. And next, a second etching step is performed to remove any remaining conductive layer not covered by the hard masking layer after the first etching step. The second etching step is performed with an etchant comprising ammonium hydroxide.

摘要翻译： 提供一种制造半导体器件的方法。 制造半导体器件的方法包括提供衬底。 接下来，依次在基板上形成绝缘层，导电层和硅化物层。 接下来，在暴露硅化物层的一部分的硅化物层上形成硬掩模层。 执行第一蚀刻步骤以去除未被硬掩模层覆盖的硅化物层和下面的导电层，从而形成栅极堆叠。 接下来，执行第二蚀刻步骤以在第一蚀刻步骤之后去除未被硬掩模层覆盖的剩余导电层。 用包含氢氧化铵的蚀刻剂进行第二蚀刻步骤。

公开(公告)号：US06964926B2

公开(公告)日：2005-11-15

申请号：US10727924

申请日：2003-12-04

申请人： Tse-Yao Huang ,  Yi-Nan Chen ,  Tzu-Ching Tsai

发明人： Tse-Yao Huang ,  Yi-Nan Chen ,  Tzu-Ching Tsai

IPC分类号： H01L21/20 ,  H01L21/308 ,  H01L21/334 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/1087 ,  H01L27/10829 ,  H01L29/66181 ,  Y10S438/942

摘要： A method of forming capacitors with geometric deep trenches. First, a substrate with a pad structure formed thereon is provided, and a first hard mask layer is formed on the pad structure. Next, a second hard mask layer is formed on the first hard mask layer. Next, a spacer layer is formed in the first opening on the first hard mask layer to expose a second opening. Next, a third hard mask layer is filled the second opening, and the spacer layer is removed. Next, the first hard mask layer is etched to expose a third opening with a salient of the first hard mask layer, with the second hard mask layer and the third hard mask layer acting as masks. Finally, the first hard mask layer, the pad structure, and the substrate are etched to form a geometric deep trench.

摘要翻译： 一种形成具有几何深沟槽的电容器的方法。 首先，提供在其上形成有衬垫结构的衬底，并且在衬垫结构上形成第一硬掩模层。 接着，在第一硬掩模层上形成第二硬掩模层。 接下来，在第一硬掩模层上的第一开口中形成间隔层以露出第二开口。 接下来，在第二开口填充第三硬掩模层，并且移除间隔层。 接下来，第一硬掩模层被蚀刻以暴露具有第一硬掩模层的凸起的第三开口，第二硬掩模层和第三硬掩模层用作掩模。 最后，蚀刻第一硬掩模层，焊盘结构和衬底以形成几何深沟槽。

公开(公告)号：US06790740B2

公开(公告)日：2004-09-14

申请号：US10375485

申请日：2003-02-27

申请人： Tse-Yao Huang ,  Tzu-Ching Tsai ,  Yi-Nan Chen

发明人： Tse-Yao Huang ,  Tzu-Ching Tsai ,  Yi-Nan Chen

IPC分类号： H01L2120

CPC分类号： H01L27/1087 ,  H01L29/66181

摘要： A process for filling a polysilicon seam. First, a semiconducting substrate or an insulating layer having a trench is provided, and a first polysilicon layer having a seam is filled in the trench. Next, the first polysilicon layer is etched to expose the seam. Next, a second polysilicon layer is formed to fill the top portion of the seam and close the seam.

摘要翻译： 一种填充多晶硅接缝的工艺。 首先，提供具有沟槽的半导体衬底或绝缘层，并且在沟槽中填充具有接缝的第一多晶硅层。 接下来，蚀刻第一多晶硅层以暴露接缝。 接下来，形成第二多晶硅层以填充接缝的顶部并闭合接缝。

公开(公告)号：US06303491B1

公开(公告)日：2001-10-16

申请号：US09283984

申请日：1999-04-02

申请人： Tzu-Ching Tsai ,  Lin-Chin Su ,  Jengping Lin ,  Tse Yao Huang

发明人： Tzu-Ching Tsai ,  Lin-Chin Su ,  Jengping Lin ,  Tse Yao Huang

IPC分类号： H01L214763

CPC分类号： H01L21/76897 ,  H01L21/76804 ,  H01L21/76831

摘要： A method for fabricating a self-aligned contact hole in accordance with the present invention is disclosed. First a conductive layer, a silicon oxide layer, and a first silicon nitride layer are formed on a silicon substrate. Next, the first silicon nitride layer, the silicon oxide layer, and the conductive layer are etched to form a trench. Then, a BPSG layer is formed over the first silicon nitride layer. A photoresist layer having an opening is defined. Then, using the photoresist layer as the masking layer, a part of BPSG layer is etched to form a self-aligned hole. Next, the photoresist layer is removed. Afterward, a second silicon nitride layer is formed and etched back to form a spacer.

摘要翻译： 公开了一种用于制造根据本发明的自对准接触孔的方法。 首先，在硅衬底上形成导电层，氧化硅层和第一氮化硅层。 接下来，蚀刻第一氮化硅层，氧化硅层和导电层以形成沟槽。 然后，在第一氮化硅层上形成BPSG层。 定义了具有开口的光刻胶层。 然后，使用光致抗蚀剂层作为掩模层，对BPSG层的一部分进行蚀刻以形成自对准孔。 接下来，去除光致抗蚀剂层。 之后，形成第二氮化硅层并将其回蚀以形成间隔物。

公开(公告)号：US07341952B2

公开(公告)日：2008-03-11

申请号：US11348626

申请日：2006-02-07

申请人： Kaan-Lu Tzou ,  Tzu-Ching Tsai ,  Yi-Nan Chen

发明人： Kaan-Lu Tzou ,  Tzu-Ching Tsai ,  Yi-Nan Chen

IPC分类号： H01L21/302

CPC分类号： H01L27/1087 ,  C03C15/00 ,  H01L21/0332 ,  H01L21/3081

摘要： A method for etching a deep trench in a substrate. A multi-layer hard mask structure is formed overlying the substrate, which includes a first hard mask layer and at least one second hard mask layer disposed thereon. The first hard mask layer is composed of a first boro-silicate glass (BSG) layer and an overlying first undoped silicon glass (USG) layer and the second is composed of a second BSG layer and an overlying second USG layer. A polysilicon layer is formed overlying the multi-layer hard mask structure and then etched to form an opening therein. The multi-layer hard mask structure and the underlying substrate under the opening are successively etched to simultaneously form the deep trench in the substrate and remove the polysilicon layer. The multi-layer hard mask structure is removed.

摘要翻译： 一种用于蚀刻衬底中的深沟槽的方法。 形成覆盖在基板上的多层硬掩模结构，其包括第一硬掩模层和设置在其上的至少一个第二硬掩模层。 第一硬掩模层由第一硼硅酸盐玻璃（BSG）层和上覆的第一未掺杂硅玻璃（USG）层组成，第二硬质掩模层由第二BSG层和第二USG层组成。 形成覆盖多层硬掩模结构的多晶硅层，然后蚀刻以形成其中的开口。 连续蚀刻多层硬掩模结构和开口下方的底层基板，同时在衬底中形成深沟槽并去除多晶硅层。 去除多层硬掩模结构。

公开(公告)号：US20060118886A1

公开(公告)日：2006-06-08

申请号：US11338330

申请日：2006-01-23

申请人： Tzu-Ching Tsai ,  Yi-Nan Chen ,  Hui-Min Mao

发明人： Tzu-Ching Tsai ,  Yi-Nan Chen ,  Hui-Min Mao

IPC分类号： H01L29/772

CPC分类号： H01L21/76897 ,  H01L21/76829 ,  H01L21/76895

摘要： A method of forming a bit line contact via. The method includes providing a substrate having a transistor with a gate electrode, drain region, and source region, forming a conductive layer overlying the drain region, conformally forming an insulating barrier layer overlying the substrate, blanketly forming a dielectric layer overlying the insulating barrier layer, and forming a via through the dielectric layer and insulating barrier layer, exposing the conductive layer.

摘要翻译： 形成位线接触通孔的方法。 该方法包括提供具有晶体管的衬底，该晶体管具有栅极，漏极区和源极区，形成覆盖漏极区的导电层，保形地形成覆盖衬底的绝缘阻挡层，覆盖在绝缘阻挡层上的绝缘层 并且通过介电层和绝缘阻挡层形成通孔，暴露导电层。

公开(公告)号：US06815356B2

公开(公告)日：2004-11-09

申请号：US10379445

申请日：2003-03-03

申请人： Tzu-Ching Tsai ,  Hsin-Jung Ho ,  Yi-Nan Chen

发明人： Tzu-Ching Tsai ,  Hsin-Jung Ho ,  Yi-Nan Chen

IPC分类号： H01L21311

CPC分类号： H01L21/76232 ,  H01L27/1087 ,  H01L29/66181

摘要： A method for forming a bottle trench in a substrate having a pad structure and a trench. First, a first insulating layer is formed in the trench, and a portion of the first insulating layer is removed to a certain depth of the trench. Next, a second insulating layer is formed in the trench, and portions of the second insulating layer on the pad structure and the sidewalls of the trench are removed. Next, an etching stop layer is formed in the trench, and a bottom portion of the etching stop layer is removed. Finally, the etching stop layer is used as a mask to remove the remaining second insulating layer and the first insulating layer.

摘要翻译： 一种在具有衬垫结构和沟槽的衬底中形成瓶沟槽的方法。 首先，在沟槽中形成第一绝缘层，并且将第一绝缘层的一部分去除到沟槽的一定深度。 接下来，在沟槽中形成第二绝缘层，并且去除衬垫结构上的第二绝缘层的部分和沟槽的侧壁。 接下来，在沟槽中形成蚀刻停止层，去除蚀刻停止层的底部。 最后，将蚀刻停止层用作掩模以去除剩余的第二绝缘层和第一绝缘层。

公开(公告)号：US20130102123A1

公开(公告)日：2013-04-25

申请号：US13276960

申请日：2011-10-19

申请人： Tzu-Ching Tsai ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Tzu-Ching Tsai ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/02

CPC分类号： H01L27/10867

摘要： A method for manufacturing a buried-strap includes: forming a trench capacitor structure in a semiconductor substrate, wherein the trench capacitor structure has a doped polysilicon layer and an isolation collar covered by the doped polysilicon layer, and a top surface of the doped polysilicon layer is lower than a top surface of the semiconductor substrate such that a first recess is formed; sequentially forming a first resist layer, a second resist layer and a third resist layer over the semiconductor substrate; sequentially patterning the third resist layer, the second resist layer and the first resist layer, forming a patterned tri-layer resist layer over the semiconductor substrate; partially removing a portion of the doped polysilicon layer exposed by the patterned tri-layer resist layer to form a second recess; removing the patterned tri-layer resist layer; and forming an insulating layer in the second recess and a portion of the first recess.

摘要翻译： 一种掩埋带的制造方法包括：在半导体衬底中形成沟槽电容器结构，其中沟槽电容器结构具有掺杂多晶硅层和由掺杂多晶硅层覆盖的隔离环，以及掺杂多晶硅层的顶表面 低于半导体衬底的顶表面，从而形成第一凹槽; 在半导体衬底上依次形成第一抗蚀剂层，第二抗蚀剂层和第三抗蚀剂层; 顺序地图案化第三抗蚀剂层，第二抗蚀剂层和第一抗蚀剂层，在半导体衬底上形成图案化的三层抗蚀剂层; 部分地去除由图案化的三层抗蚀剂层暴露的部分掺杂多晶硅层以形成第二凹槽; 去除图案化的三层抗蚀剂层; 以及在所述第二凹部中形成绝缘层和所述第一凹部的一部分。

公开(公告)号：US07195975B2

公开(公告)日：2007-03-27

申请号：US10714001

申请日：2003-11-14

申请人： Tzu-Ching Tsai ,  Yi-Nan Chen ,  Hui-Min Mao

发明人： Tzu-Ching Tsai ,  Yi-Nan Chen ,  Hui-Min Mao

IPC分类号： H01L21/8242 ,  H01L21/20

CPC分类号： H01L21/76897 ,  H01L21/76829 ,  H01L21/76895

摘要： A method of forming a bit line contact via. The method includes providing a substrate having a transistor with a gate electrode, drain region, and source region, forming a conductive layer overlying the drain region, conformally forming an insulating barrier layer overlying the substrate, blanketly forming a dielectric layer overlying the insulating barrier layer, and forming a via through the dielectric layer and insulating barrier layer, exposing the conductive layer.

摘要翻译： 形成位线接触通孔的方法。 该方法包括提供具有晶体管的衬底，该晶体管具有栅极，漏极区和源极区，形成覆盖漏极区的导电层，保形地形成覆盖衬底的绝缘阻挡层，覆盖在绝缘阻挡层上的绝缘层 并且通过介电层和绝缘阻挡层形成通孔，暴露导电层。

公开(公告)号：US06924204B2

公开(公告)日：2005-08-02

申请号：US10605304

申请日：2003-09-22

申请人： Tzu-Ching Tsai ,  Yi-Nan Chen

发明人： Tzu-Ching Tsai ,  Yi-Nan Chen

IPC分类号： H01L21/00 ,  H01L21/20 ,  H01L21/76 ,  H01L21/8242

CPC分类号： H01L27/1087

摘要： A method for fabricating a buried plate of a deep trench capacitor is described. A substrate having a deep trench therein is provided. A doped layer is formed on the surface of the deep trench and a material layer is formed on the doped layer. A passivation layer is formed on the sidewall of the deep trench that is not covered by the material layer. After removing the material layer, a thermal process is conducted to drive-in the dopants in the doped layer to the substrate to form a doped region, wherein the doped region serves as a buried plate of the deep trench capacitor. The doped layer also reacts with the substrate to form an oxide layer. After removing the oxide layer, a bottle-shaped deep trench is formed.

摘要翻译： 描述了制造深沟槽电容器的掩埋板的方法。 提供其中具有深沟槽的衬底。 在深沟槽的表面上形成掺杂层，并且在掺杂层上形成材料层。 钝化层形成在深沟槽的不被材料层覆盖的侧壁上。 在去除材料层之后，进行热处理以将掺杂层中的掺杂剂驱入衬底以形成掺杂区域，其中掺杂区域用作深沟槽电容器的掩埋板。 掺杂层也与衬底反应以形成氧化物层。 在去除氧化物层之后，形成瓶形深沟槽。