公开(公告)号：US20060127680A1

公开(公告)日：2006-06-15

申请号：US11348626

申请日：2006-02-07

申请人： Kaan-Lu Tzou ,  Tzu-Ching Tsai ,  Yi-Nan Chen

发明人： Kaan-Lu Tzou ,  Tzu-Ching Tsai ,  Yi-Nan Chen

IPC分类号： B32B17/06 ,  B32B9/00

CPC分类号： H01L27/1087 ,  C03C15/00 ,  H01L21/0332 ,  H01L21/3081

摘要： A method for etching a deep trench in a substrate. A multi-layer hard mask structure is formed overlying the substrate, which includes a first hard mask layer and at least one second hard mask layer disposed thereon. The first hard mask layer is composed of a first boro-silicate glass (BSG) layer and an overlying first undoped silicon glass (USG) layer and the second is composed of a second BSG layer and an overlying second USG layer. A polysilicon layer is formed overlying the multi-layer hard mask structure and then etched to form an opening therein. The multi-layer hard mask structure and the underlying substrate under the opening are successively etched to simultaneously form the deep trench in the substrate and remove the polysilicon layer. The multi-layer hard mask structure is removed.

公开(公告)号：US07029753B2

公开(公告)日：2006-04-18

申请号：US10727790

申请日：2003-12-04

申请人： Kaan-Lu Tzou ,  Tzu-Ching Tsai ,  Yi-Nan Chen

发明人： Kaan-Lu Tzou ,  Tzu-Ching Tsai ,  Yi-Nan Chen

IPC分类号： B23B17/06

CPC分类号： H01L27/1087 ,  C03C15/00 ,  H01L21/0332 ,  H01L21/3081

摘要： A method for etching a deep trench in a substrate. A multi-layer hard mask structure is formed overlying the substrate, which includes a first hard mask layer and at least one second hard mask layer disposed thereon. The first hard mask layer is composed of a first boro-silicate glass (BSG) layer and an overlying first undoped silicon glass (USG) layer and the second is composed of a second BSG layer and an overlying second USG layer. A polysilicon layer is formed overlying the multi-layer hard mask structure and then etched to form an opening therein. The multi-layer hard mask structure and the underlying substrate under the opening are successively etched to simultaneously form the deep trench in the substrate and remove the polysilicon layer. The multi-layer hard mask structure is removed.

摘要翻译： 一种用于蚀刻衬底中的深沟槽的方法。 形成覆盖在基板上的多层硬掩模结构，其包括第一硬掩模层和设置在其上的至少一个第二硬掩模层。 第一硬掩模层由第一硼硅酸盐玻璃（BSG）层和上覆的第一未掺杂硅玻璃（USG）层组成，第二硬质掩模层由第二BSG层和第二USG层组成。 形成覆盖多层硬掩模结构的多晶硅层，然后蚀刻以形成其中的开口。 连续蚀刻多层硬掩模结构和开口下方的底层基板，同时在衬底中形成深沟槽并去除多晶硅层。 去除多层硬掩模结构。

公开(公告)号：US06964926B2

公开(公告)日：2005-11-15

申请号：US10727924

申请日：2003-12-04

申请人： Tse-Yao Huang ,  Yi-Nan Chen ,  Tzu-Ching Tsai

发明人： Tse-Yao Huang ,  Yi-Nan Chen ,  Tzu-Ching Tsai

IPC分类号： H01L21/20 ,  H01L21/308 ,  H01L21/334 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/1087 ,  H01L27/10829 ,  H01L29/66181 ,  Y10S438/942

摘要： A method of forming capacitors with geometric deep trenches. First, a substrate with a pad structure formed thereon is provided, and a first hard mask layer is formed on the pad structure. Next, a second hard mask layer is formed on the first hard mask layer. Next, a spacer layer is formed in the first opening on the first hard mask layer to expose a second opening. Next, a third hard mask layer is filled the second opening, and the spacer layer is removed. Next, the first hard mask layer is etched to expose a third opening with a salient of the first hard mask layer, with the second hard mask layer and the third hard mask layer acting as masks. Finally, the first hard mask layer, the pad structure, and the substrate are etched to form a geometric deep trench.

摘要翻译： 一种形成具有几何深沟槽的电容器的方法。 首先，提供在其上形成有衬垫结构的衬底，并且在衬垫结构上形成第一硬掩模层。 接着，在第一硬掩模层上形成第二硬掩模层。 接下来，在第一硬掩模层上的第一开口中形成间隔层以露出第二开口。 接下来，在第二开口填充第三硬掩模层，并且移除间隔层。 接下来，第一硬掩模层被蚀刻以暴露具有第一硬掩模层的凸起的第三开口，第二硬掩模层和第三硬掩模层用作掩模。 最后，蚀刻第一硬掩模层，焊盘结构和衬底以形成几何深沟槽。

公开(公告)号：US20050042871A1

公开(公告)日：2005-02-24

申请号：US10727790

申请日：2003-12-04

申请人： Kaan-Lu Tzou ,  Tzu-Ching Tsai ,  Yi-Nan Chen

发明人： Kaan-Lu Tzou ,  Tzu-Ching Tsai ,  Yi-Nan Chen

IPC分类号： C03C15/00 ,  H01L21/033 ,  H01L21/308 ,  H01L21/8242 ,  B32B17/06 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L27/1087 ,  C03C15/00 ,  H01L21/0332 ,  H01L21/3081

摘要： A method for etching a deep trench in a substrate. A multi-layer hard mask structure is formed overlying the substrate, which includes a first hard mask layer and at least one second hard mask layer disposed thereon. The first hard mask layer is composed of a first boro-silicate glass (BSG) layer and an overlying first undoped silicon glass (USG) layer and the second is composed of a second BSG layer and an overlying second USG layer. A polysilicon layer is formed overlying the multi-layer hard mask structure and then etched to form an opening therein. The multi-layer hard mask structure and the underlying substrate under the opening are successively etched to simultaneously form the deep trench in the substrate and remove the polysilicon layer. The multi-layer hard mask structure is removed.

摘要翻译： 一种用于蚀刻衬底中的深沟槽的方法。 形成覆盖在基板上的多层硬掩模结构，其包括第一硬掩模层和设置在其上的至少一个第二硬掩模层。 第一硬掩模层由第一硼硅酸盐玻璃（BSG）层和上覆的第一未掺杂硅玻璃（USG）层组成，第二硬质掩模层由第二BSG层和第二USG层组成。 形成覆盖多层硬掩模结构的多晶硅层，然后蚀刻以形成其中的开口。 连续蚀刻多层硬掩模结构和开口下方的底层基板，同时在衬底中形成深沟槽并去除多晶硅层。 去除多层硬掩模结构。

公开(公告)号：US08335119B1

公开(公告)日：2012-12-18

申请号：US13276952

申请日：2011-10-19

申请人： Tzu-Ching Tsai ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Tzu-Ching Tsai ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： G11C7/00

CPC分类号： H01L27/10847 ,  G11C11/40 ,  G11C29/50016 ,  G11C2029/0403 ,  H01L22/12 ,  H01L22/20 ,  H01L27/10861

摘要： A method of inspecting a memory cell is provided, including: providing a semiconductor substrate with a capacitor formed therein and a transistor formed thereon, wherein the transistor is electrically connected to the capacitor; inspecting a size of a top surface of the capacitor and a pitch between the capacitor and the transistor electrically connected thereto by an optical measuring system, thereby obtaining a first measurement data and a second measurement data; and comparing the first and second measurement data with designed specifications of the capacitor and transistor, thereby determining functionality of the memory cell comprising the capacitor and the transistor.

摘要翻译： 提供了一种检查存储单元的方法，包括：提供其中形成有电容器的半导体衬底和形成在其上的晶体管，其中晶体管电连接到电容器; 通过光学测量系统检查电容器的顶表面的大小和电容器与与其电连接的晶体管之间的间距，从而获得第一测量数据和第二测量数据; 以及将第一和第二测量数据与电容器和晶体管的设计规范进行比较，从而确定包括电容器和晶体管的存储单元的功能。

公开(公告)号：US07807558B2

公开(公告)日：2010-10-05

申请号：US11933732

申请日：2007-11-01

申请人： Tzu-Ching Tsai ,  Tse-Yao Huang ,  Yi-Nan Chen

发明人： Tzu-Ching Tsai ,  Tse-Yao Huang ,  Yi-Nan Chen

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/02063 ,  H01L21/02071 ,  H01L21/32137

摘要： A method of fabricating a semiconductor device is provided. The method of fabricating the semiconductor device comprises providing a substrate. Next, an insulating layer, a conductive layer and a silicide layer are formed on the substrate in sequence. Next, a hard masking layer is formed on the silicide layer exposing a portion of the silicide layer. A first etching step is performed to remove the silicide layer and the underlying conductive layer which are not covered by the hard masking layer, thereby forming a gate stack. And next, a second etching step is performed to remove any remaining conductive layer not covered by the hard masking layer after the first etching step. The second etching step is performed with an etchant comprising ammonium hydroxide.

摘要翻译： 提供一种制造半导体器件的方法。 制造半导体器件的方法包括提供衬底。 接下来，依次在基板上形成绝缘层，导电层和硅化物层。 接下来，在暴露硅化物层的一部分的硅化物层上形成硬掩模层。 执行第一蚀刻步骤以去除未被硬掩模层覆盖的硅化物层和下面的导电层，从而形成栅极堆叠。 接下来，执行第二蚀刻步骤以在第一蚀刻步骤之后去除未被硬掩模层覆盖的剩余导电层。 用包含氢氧化铵的蚀刻剂进行第二蚀刻步骤。

公开(公告)号：US20070020844A1

公开(公告)日：2007-01-25

申请号：US11490206

申请日：2006-07-19

申请人： Yi-Nan Chen ,  Tzu-Ching Tsai

发明人： Yi-Nan Chen ,  Tzu-Ching Tsai

IPC分类号： H01L21/8242 ,  H01L29/94

CPC分类号： H01L27/10888 ,  H01L27/10885

摘要： A damascene process. A substrate covered by a dielectric layer and an overlying polysilicon masking layer with an opening exposing the underlying dielectric layer is provided. The exposed dielectric layer is etched to form a damascene opening therein and a portion of polysilicon masking layer remains on the dielectric layer. The remaining polysilicon masking layer is completely transformed into a metal polycide layer and then removed. A method for fabricating a bit line of a memory device is also disclosed.

摘要翻译： 一个镶嵌过程。 提供了由电介质层覆盖的衬底和具有暴露下面介电层的开口的上覆多晶硅掩模层。 蚀刻暴露的介电层以在其中形成镶嵌开口，并且一部分多晶硅掩模层保留在电介质层上。 剩余的多晶硅掩模层完全转变为金属多晶硅化物层，然后除去。 还公开了一种用于制造存储器件的位线的方法。

公开(公告)号：US07026207B2

公开(公告)日：2006-04-11

申请号：US10715611

申请日：2003-11-18

申请人： Tzu-Ching Tsai ,  Yi-Nan Chen

发明人： Tzu-Ching Tsai ,  Yi-Nan Chen

IPC分类号： H01L21/8238

CPC分类号： H01L27/10888 ,  H01L21/76877 ,  H01L27/10894

摘要： A method of filling a bit line contact via. The method includes providing a substrate having a device region and periphery region, the device region having a transistor, having a gate electrode, drain region, and source region, on the substrate, forming a dielectric layer overlying the substrate, the dielectric layer having a bit line contact via exposing the drain region, and periphery contact via exposing the periphery region, forming a doped conductive layer, lower than the dielectric layer, overlying the drain region, conformally forming a barrier layer overlying the dielectric layer, doped conductive layer, and periphery region, and forming a first conductive layer filling the bit line contact via and periphery contact via.

摘要翻译： 填充位线接触通孔的方法。 该方法包括提供具有器件区域和外围区域的衬底，器件区域具有在衬底上的栅电极，漏极区和源极区的晶体管，形成覆盖衬底的电介质层，电介质层具有 通过暴露漏极区域和周边接触，通过暴露外围区域形成位线接触，形成覆盖漏极区域的低于介电层的掺杂导电层，保形地形成覆盖在电介质层上的阻挡层，掺杂导电层和 并且形成填充位线接触通孔和周边接触通孔的第一导电层。

公开(公告)号：US06946344B2

公开(公告)日：2005-09-20

申请号：US10620743

申请日：2003-07-16

申请人： Shih-Chung Chou ,  Yi-Nan Chen ,  Tzu-Ching Tsai

发明人： Shih-Chung Chou ,  Yi-Nan Chen ,  Tzu-Ching Tsai

IPC分类号： H01L21/00 ,  H01L21/20 ,  H01L21/8242

CPC分类号： H01L27/10861 ,  H01L27/1087 ,  Y10T29/41

摘要： A method for forming a trench capacitor. A semiconductor substrate with a trench is provided, and a trench capacitor is formed in the trench with a storage node and a node dielectric layer. The top portion of the trench is ion implanted to a predetermined angle to form an ion doped area on a sidewall of the top portion of the trench and a top surface of the trench capacitor. The ion doped area is oxidized to form an oxide layer. A sidewall semiconductor layer is formed on another sidewall using the oxide layer as a mask, and then the oxide layer is removed. A barrier layer is conformally formed on the surface of the trench, and the trench is filled with a conducting layer.

摘要翻译： 一种形成沟槽电容器的方法。 提供具有沟槽的半导体衬底，并且沟槽电容器在沟槽中形成有存储节点和节点电介质层。 将沟槽的顶部离子注入预定角度，以在沟槽顶部的侧壁和沟槽电容器的顶表面上形成离子掺杂区域。 离子掺杂区域被氧化形成氧化物层。 使用氧化物层作为掩模在另一侧壁上形成侧壁半导体层，然后除去氧化物层。 在沟槽的表面上保形地形成阻挡层，并且沟槽填充有导电层。

公开(公告)号：US06709975B2

公开(公告)日：2004-03-23

申请号：US10222349

申请日：2002-08-16

申请人： Hui Min Mao ,  Yi-Nan Chen ,  Tzu-Ching Tsai

发明人： Hui Min Mao ,  Yi-Nan Chen ,  Tzu-Ching Tsai

IPC分类号： H01L214763

CPC分类号： H01L21/76837 ,  H01L21/76885

摘要： A method of forming inter-metal dielectric (IMD). A substrate having a patterned metal layer thereon has at least one opening to expose the substrate. The opening has an aspect ratio of 3.5˜4.5. Next, the opening is filled with a first dielectric layer, and voids are formed in the upper portion of the first dielectric layer due to the high aspect ratio opening. Thereafter, the first dielectric layer is etched to leave the first dielectric layer with a predetermined height in the opening without voids. Finally, a second dielectric layer is formed on the first dielectric layer to completely fill the opening.

摘要翻译： 一种形成金属间电介质（IMD）的方法。 其上具有图案化金属层的衬底具有至少一个露出衬底的开口。 开口的长宽比为3.5〜4.5。 接下来，开口填充有第一电介质层，并且由于高纵横比开口，在第一电介质层的上部形成空隙。 此后，蚀刻第一电介质层以使第一介电层在开口中具有预定的高度而没有空隙。 最后，在第一电介质层上形成第二电介质层以完全填充开口。