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公开(公告)号：US10199258B2
公开(公告)日：2019-02-05
申请号：US15384940
申请日：2016-12-20
Inventor： Chieh-Te Chen , Hsien-Shih Chu , Ming-Feng Kuo , Fu-Che Lee , Chien-Ting Ho , Chiung-Lin Hsu , Feng-Yi Chang , Yi-Wang Zhan , Li-Chiang Chen , Chien-Cheng Tsai , Chin-Hsin Chiu
IPC: H01L21/762 , H01L21/308
Abstract: A method of fabricating an isolation structure is provided. A first oxide layer and a first, second, and third hard mask layers are formed on a substrate. A patterned third hard mask layer is formed. Second oxide layers are formed on sidewalls of the patterned third hard mask layer and a fourth hard mask layer is formed between the second oxide layers. The second oxide layers and the second hard mask layer are removed using the patterned third hard mask layer and the fourth hard mask layer as a mask, to form a patterned second hard mask layer. The patterned third hard mask layer and the fourth hard mask layer are removed. A portion of the patterned second hard mask layer is removed to form trench patterns. A patterned first hard mask layer and first oxide layer, and trenches located in the substrate are defined. An isolation material is formed.
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公开(公告)号：US09548216B1
公开(公告)日：2017-01-17
申请号：US14809270
申请日：2015-07-26
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yu-Te Chen , Chia-Hsun Tseng , En-Chiuan Liou , Chiung-Lin Hsu , Meng-Lin Tsai , Jan-Fu Yang , Yu-Ting Hung , Shin-Feng Su
IPC: H01L21/76 , H01L21/321 , H01L21/225 , H01L21/3205 , H01L21/3105
CPC classification number: H01L21/2253 , H01L21/30604 , H01L21/3065 , H01L21/823412 , H01L21/823431 , H01L21/823807 , H01L21/823821
Abstract: A method of adjusting channel widths of semiconductive devices includes providing a substrate divided into a first region and a second region, wherein the substrate comprises numerous fins. A first implantation process is performed on the fins within the first region. Then, a second implantation process is performed on the fins within the second region, wherein the first implantation process and the second implantation process are different from each other in at least one of the conditions comprising dopant species, dopant dosage or implantation energy. After that, part of the fins within the first region and the second region are removed simultaneously to form a plurality of first recesses within the first region and a plurality of second recesses within the second region. Finally, a first epitaxial layer and a second epitaxial layer are formed to fill up each first recess and each second recess, respectively.
Abstract translation: 调整半导体器件的沟道宽度的方法包括提供分成第一区域和第二区域的衬底，其中衬底包括多个鳍片。 在第一区域内的翅片上执行第一注入工艺。 然后，对第二区域内的翅片执行第二注入工艺，其中第一注入工艺和第二注入工艺在包括掺杂剂种类，掺杂剂剂量或注入能量的至少一个条件中彼此不同。 之后，同时去除第一区域和第二区域内的部分散热片，以在第一区域内形成多个第一凹槽，在第二区域内形成多个第二凹槽。 最后，形成第一外延层和第二外延层以分别填充每个第一凹槽和每个第二凹槽。
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公开(公告)号：US20180108563A1
公开(公告)日：2018-04-19
申请号：US15384940
申请日：2016-12-20
Inventor： Chieh-Te Chen , Hsien-Shih Chu , Ming-Feng Kuo , Fu-Che Lee , Chien-Ting Ho , Chiung-Lin Hsu , Feng-Yi Chang , Yi-Wang Zhan , Li-Chiang Chen , Chien-Cheng Tsai , Chin-Hsin Chiu
IPC: H01L21/762 , H01L21/308
CPC classification number: H01L21/76224 , H01L21/3081 , H01L21/762
Abstract: A method of fabricating an isolation structure is provided. A first oxide layer and a first, second, and third hard mask layers are formed on a substrate. A patterned third hard mask layer is formed. Second oxide layers are formed on sidewalls of the patterned third hard mask layer and a fourth hard mask layer is formed between the second oxide layers. The second oxide layers and the second hard mask layer are removed using the patterned third hard mask layer and the fourth hard mask layer as a mask, to form a patterned second hard mask layer. The patterned third hard mask layer and the fourth hard mask layer are removed. A portion of the patterned second hard mask layer is removed to form trench patterns. A patterned first hard mask layer and first oxide layer, and trenches located in the substrate are defined. An isolation material is formed.
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公开(公告)号：US20170025286A1
公开(公告)日：2017-01-26
申请号：US14809270
申请日：2015-07-26
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Yu-Te Chen , Chia-Hsun Tseng , En-Chiuan Liou , Chiung-Lin Hsu , Meng-Lin Tsai , Jan-Fu Yang , Yu-Ting Hung , Shin-Feng Su
IPC: H01L21/321 , H01L21/3205 , H01L21/3105 , H01L21/225
CPC classification number: H01L21/2253 , H01L21/30604 , H01L21/3065 , H01L21/823412 , H01L21/823431 , H01L21/823807 , H01L21/823821
Abstract: A method of adjusting channel widths of semiconductive devices includes providing a substrate divided into a first region and a second region, wherein the substrate comprises numerous fins. A first implantation process is performed on the fins within the first region. Then, a second implantation process is performed on the fins within the second region, wherein the first implantation process and the second implantation process are different from each other in at least one of the conditions comprising dopant species, dopant dosage or implantation energy. After that, part of the fins within the first region and the second region are removed simultaneously to form a plurality of first recesses within the first region and a plurality of second recesses within the second region. Finally, a first epitaxial layer and a second epitaxial layer are formed to fill up each first recess and each second recess, respectively.
Abstract translation: 调整半导体器件的沟道宽度的方法包括提供分成第一区域和第二区域的衬底，其中衬底包括多个鳍片。 在第一区域内的翅片上执行第一注入工艺。 然后，对第二区域内的翅片执行第二注入工艺，其中第一注入工艺和第二注入工艺在包括掺杂剂种类，掺杂剂剂量或注入能量的至少一个条件中彼此不同。 之后，同时去除第一区域和第二区域内的部分散热片，以在第一区域内形成多个第一凹槽，在第二区域内形成多个第二凹槽。 最后，形成第一外延层和第二外延层以分别填充每个第一凹槽和每个第二凹槽。
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