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    SEMICONDUCTOR PROCESS
    2.
    发明申请
    SEMICONDUCTOR PROCESS 审中-公开

    公开(公告)号：US20170352736A1

    公开(公告)日：2017-12-07

    申请号：US15682525

    申请日：2017-08-21

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： YI CHUEN ENG ,  Teng-Chuan Hu ,  I-Chang Wang ,  Wei-Chih Chen ,  Hsiu-Kuan Hsu

    IPC: H01L29/423 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06

    CPC classification number: H01L29/42356 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

    Abstract: A fin-shaped field effect transistor includes a substrate and a gate. The substrate includes an active area, where the active area includes a fin structure having at least an extension part protruding from the fin structure. The gate is disposed over the fin structure and directly on the extension part. The present invention also provides a planar field effect transistor including a substrate and a gate. The substrate includes an active area, where the active area includes a frame area and a penetrating area penetrating through the frame area. The gate is disposed over the active area, where the gate is directly disposed on the penetrating area, and the frame area at least at a side of the gate constitutes a source/drain surrounding an isolation island.

    Spacer scheme for semiconductor device
    3.
    发明授权
    Spacer scheme for semiconductor device 有权
    半导体器件的间隔方案

    公开(公告)号：US09269811B2

    公开(公告)日：2016-02-23

    申请号：US14583211

    申请日：2014-12-26

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ling-Chun Chou ,  I-Chang Wang ,  Ching-Wen Hung

    IPC: H01L31/119 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/165

    CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

    Abstract: A manufacturing method for a semiconductor device includes providing a substrate having at least agate structure formed thereon and a first spacer formed on sidewalls of the gate structure, performing an ion implantation to implant dopants into the substrate, forming a disposal spacer having at least a carbon-containing layer on the sidewalls of the gate structure, the carbon-containing layer contacting the first spacer, and performing a thermal treatment to form a protecting layer between the carbon-containing layer and the first spacer.

    Abstract translation: 一种用于半导体器件的制造方法，包括提供至少具有玛瑙结构的基板和形成在栅极结构的侧壁上的第一间隔物，进行离子注入以将掺杂剂注入衬底中，形成具有至少一个碳 所述含碳层与所述第一间隔物接触，并进行热处理以在所述含碳层和所述第一间隔物之间​​形成保护层。

    Planar field effect transistor
    4.
    发明授权
    Planar field effect transistor 有权

    公开(公告)号：US10068979B2

    公开(公告)日：2018-09-04

    申请号：US15677035

    申请日：2017-08-15

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Yi Chuen Eng ,  Teng-Chuan Hu ,  I-Chang Wang ,  Wei-Chih Chen ,  Hsiu-Kuan Hsu

    IPC: H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

    Abstract: A fin-shaped field effect transistor includes a substrate and a gate. The substrate includes an active area, where the active area includes a fin structure having at least an extension part protruding from the fin structure. The gate is disposed over the fin structure and directly on the extension part. The present invention also provides a planar field effect transistor including a substrate and a gate. The substrate includes an active area, where the active area includes a frame area and a penetrating area penetrating through the frame area. The gate is disposed over the active area, where the gate is directly disposed on the penetrating area, and the frame area at least at a side of the gate constitutes a source/drain surrounding an isolation island.

    SEMICONDUCTOR DEVICE
    7.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20150108553A1

    公开(公告)日：2015-04-23

    申请号：US14583211

    申请日：2014-12-26

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Ling-Chun Chou ,  I-Chang Wang ,  Ching-Wen Hung

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

    Abstract: A manufacturing method for a semiconductor device includes providing a substrate having at least agate structure formed thereon and a first spacer formed on sidewalls of the gate structure, performing an ion implantation to implant dopants into the substrate, forming a disposal spacer having at least a carbon-containing layer on the sidewalls of the gate structure, the carbon-containing layer contacting the first spacer, and performing a thermal treatment to form a protecting layer between the carbon-containing layer and the first spacer.

    Abstract translation: 一种用于半导体器件的制造方法，包括提供至少具有玛瑙结构的基板和形成在栅极结构的侧壁上的第一间隔物，进行离子注入以将掺杂剂注入衬底中，形成具有至少一个碳 所述含碳层与所述第一间隔物接触，并进行热处理以在所述含碳层和所述第一间隔物之间​​形成保护层。

    STRAINED SILICON STRUCTURE
    8.
    发明申请
    STRAINED SILICON STRUCTURE 有权
    应变硅结构

    公开(公告)号：US20130292775A1

    公开(公告)日：2013-11-07

    申请号：US13936214

    申请日：2013-07-08

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Guang-Yaw Hwang ,  Ling-Chun Chou ,  I-Chang Wang ,  Shin-Chuan Huang ,  Jiunn-Hsiung Liao ,  Shin-Chi Chen ,  Pau-Chung Lin ,  Chiu-Hsien Yeh ,  Chin-Cheng Chien ,  Chieh-Te Chen

    IPC: H01L27/088

    CPC classification number: H01L27/088 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

    Abstract: A strained silicon substrate structure includes a first transistor and a second transistor disposed on a substrate. The first transistor includes a first gate structure and two first source/drain regions disposed at two sides of the first gate structure. A first source/drain to gate distance is between each first source/drain region and the first gate structure. The second transistor includes a second gate structure and two source/drain doped regions disposed at two side of the second gate structure. A second source/drain to gate distance is between each second source/drain region and the second gate structure. The first source/drain to gate distance is smaller than the second source/drain to gate distance.

    Abstract translation: 应变硅衬底结构包括设置在衬底上的第一晶体管和第二晶体管。 第一晶体管包括第一栅极结构和设置在第一栅极结构的两侧的两个第一源极/漏极区域。 第一源极/漏极到栅极间距在每个第一源极/漏极区域和第一栅极结构之间。 第二晶体管包括第二栅极结构和设置在第二栅极结构的两侧的两个源极/漏极掺杂区域。 第二源极/漏极到栅极间距在每个第二源极/漏极区域和第二栅极结构之间。 第一源极/漏极到栅极距离小于第二源极/漏极到栅极距离。

    SEMICONDUCTOR PROCESS, PLANAR FIELD EFFECT TRANSISTOR AND FIN-SHAPED FIELD EFFECT TRANSISTOR
    10.
    发明申请
    SEMICONDUCTOR PROCESS, PLANAR FIELD EFFECT TRANSISTOR AND FIN-SHAPED FIELD EFFECT TRANSISTOR 有权
    半导体工艺，平面场效应晶体管和精细形状场效应晶体管

    公开(公告)号：US20170069730A1

    公开(公告)日：2017-03-09

    申请号：US14877926

    申请日：2015-10-07

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： YI CHUEN ENG ,  Teng-Chuan Hu ,  I-Chang Wang ,  Wei-Chih Chen ,  Hsiu-Kuan Hsu

    IPC: H01L29/423 ,  H01L29/06 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66

    CPC classification number: H01L29/42356 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

    Abstract: A fin-shaped field effect transistor includes a substrate and a gate. The substrate includes an active area, where the active area includes a fin structure having at least an extension part protruding from the fin structure. The gate is disposed over the fin structure and directly on the extension part. The present invention also provides a planar field effect transistor including a substrate and a gate. The substrate includes an active area, where the active area includes a frame area and a penetrating area penetrating through the frame area. The gate is disposed over the active area, where the gate is directly disposed on the penetrating area, and the frame area at least at a side of the gate constitutes a source/drain surrounding an isolation island.

    Abstract translation: 鳍状场效应晶体管包括衬底和栅极。 基板包括有源区域，其中有源区域包括具有至少一个从翅片结构突出的延伸部分的翅片结构。 门设置在翅片结构上并直接在延伸部分上。 本发明还提供一种包括衬底和栅极的平面场效应晶体管。 基板包括有源区域，其中有源区域包括框架区域和贯穿框架区域的穿透区域。 栅极设置在有源区域上，其中栅极直接设置在穿透区域上，并且至少在栅极侧的框架区域构成围绕隔离岛的源极/漏极。

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