-
公开(公告)号：US10290736B2
公开(公告)日：2019-05-14
申请号：US15872996
申请日：2018-01-17
Inventor： Kai-Ping Chen , Li-Wei Feng , Kuei-Hsuan Yu , Chiu-Hsien Yeh
IPC: H01L29/78 , H01L29/423 , H01L27/108
Abstract: A semiconductor device and a method of forming the same are provided. A substrate is provided. A trench is formed in the substrate and a conductive material is formed filling the trench. A portion of the conductive material filling an upper portion of the trench is removed to expose an upper surface of the substrate and an upper corner and an upper sidewall of the trench. A doping process is performed to form a doped region in the substrate along the exposed upper surface of the substrate and the exposed upper corner and upper sidewall of the trench. The doped region has an upside-down L shape.
-
公开(公告)号：US10151048B1
公开(公告)日：2018-12-11
申请号：US15825127
申请日：2017-11-29
Inventor： Wan-Chi Wu , Hui-Ling Chuang , Chih-Chi Cheng , Chiu-Hsien Yeh , Chien-Cheng Tsai , Hung-Jung Yan
IPC: H01L21/00 , C30B25/18 , H01L27/108 , G11C11/4094 , H01L21/02 , G11C11/4097
Abstract: A manufacturing method of an epitaxial contact structure in a semiconductor memory device includes the following steps. A recess is formed in a semiconductor substrate by an etching process. An etching defect is formed in the recess by the etching process. An oxidation process is performed after the etching process. An oxide layer is formed in the recess by the oxidation process, and the etching defect is encompassed by the oxide layer. A cleaning process is performed after the oxidation process. The oxide layer and the etching defect encompassed by the oxide layer are removed by the cleaning process. An epitaxial growth process is performed to form an epitaxial contact structure in the recess after the cleaning process.
-
公开(公告)号：US09685383B2
公开(公告)日：2017-06-20
申请号：US14711752
申请日：2015-05-13
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chiu-Hsien Yeh , Zhen Wu , Yen-Cheng Chang , Yu-Ting Tseng
IPC: H01L21/321 , H01L21/283 , H01L21/308 , H01L21/8238 , H01L21/311 , H01L21/02
CPC classification number: H01L21/823821 , H01L21/02041 , H01L21/28088 , H01L21/31133 , H01L29/4966 , H01L29/517 , H01L29/66545
Abstract: A method of forming a semiconductor device includes following steps. First of all, a first work function layer is formed on a substrate. Next, a first patterned photoresist layer is formed on the first work function layer. Then, the first work function layer is partially removed by using the first patterned photoresist layer as a mask to form a patterned first work function layer. Subsequently, the first patterned photoresist layer is removed by providing radical oxygen.
-
公开(公告)号：US10043882B2
公开(公告)日：2018-08-07
申请号：US15863990
申请日：2018-01-08
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Po-Wen Su , Zhen Wu , Hsiao-Pang Chou , Chiu-Hsien Yeh , Shui-Yen Lu , Jian-Wei Chen
IPC: H01L29/51 , H01L29/40 , H01L29/423 , H01L21/82 , H01L21/8234 , H01L27/088 , H01L29/66
Abstract: A method of forming a semiconductor device includes the following steps. A substrate is provided, and the substrate has a first region. A barrier layer is then formed on the first region of the substrate. A first work function layer is formed on the barrier layer. An upper half portion of the first work function layer is converted into a non-volatile material layer. The non-volatile material layer is removed and a lower half portion of the first work function layer is kept.
-
公开(公告)号：US20180212055A1
公开(公告)日：2018-07-26
申请号：US15872996
申请日：2018-01-17
Inventor： Kai-Ping Chen , Li-Wei Feng , Kuei-Hsuan Yu , Chiu-Hsien Yeh
IPC: H01L29/78 , H01L27/108 , H01L29/423
CPC classification number: H01L29/7827 , H01L27/10823 , H01L27/10876 , H01L27/10888 , H01L27/10891 , H01L29/4236
Abstract: A semiconductor device and a method of forming the same are provided. A substrate is provided. A trench is formed in the substrate and a conductive material is formed filling the trench. A portion of the conductive material filling an upper portion of the trench is removed to expose an upper surface of the substrate and an upper corner and an upper sidewall of the trench. A doping process is performed to form a doped region in the substrate along the exposed upper surface of the substrate and the exposed upper corner and upper sidewall of the trench. The doped region has an upside-down L shape.
-
Patent Agency Ranking
公开(公告)号：US10026827B2
公开(公告)日：2018-07-17
申请号：US15095154
申请日：2016-04-10
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Zhen Wu , Chiu-Hsien Yeh , Po-Wen Su , Kuan-Ying Lai
IPC: H01L29/66 , H01L21/02 , H01L21/304 , H01L21/768 , H01L21/28
Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first organic layer on the substrate; patterning the first organic layer to form an opening; forming a second organic layer in the opening; and removing the first organic layer to form a patterned second organic layer on the substrate.
-
公开(公告)号：US09281201B2
公开(公告)日：2016-03-08
申请号：US14029824
申请日：2013-09-18
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Ted Ming-Lang Guo , Chiu-Hsien Yeh , Chin-Cheng Chien , Chun-Yuan Wu
IPC: H01L21/28 , H01L21/8238 , H01L29/49 , H01L29/66 , H01L29/78 , H01L21/321 , H01L21/3213
CPC classification number: H01L21/28176 , H01L21/321 , H01L21/32134 , H01L21/823842 , H01L29/4966 , H01L29/66545 , H01L29/7833
Abstract: A method of manufacturing a semiconductor device having a metal gate is provided. A substrate having a first conductive type transistor and a second conductive type transistor formed thereon is provided. The first conductive type transistor has a first trench and the second conductive type transistor has a second trench. A first work function layer is formed in the first trench. A hardening process is performed for the first work function layer. A softening process is performed for a portion of the first work function layer. A pull back step is performed to remove the portion of the first work function layer. A second work function layer is formed in the second trench. A low resistive metal layer is formed in the first trench and the second trench.
Abstract translation: 提供一种制造具有金属栅极的半导体器件的方法。 提供具有形成在其上的第一导电型晶体管和第二导电型晶体管的衬底。 第一导电型晶体管具有第一沟槽，第二导电型晶体管具有第二沟槽。 在第一沟槽中形成第一功函数层。 对第一功函数层进行硬化处理。 对第一功函数层的一部分进行软化处理。 执行拉回步骤以去除第一功函数层的部分。 在第二沟槽中形成第二功函数层。 在第一沟槽和第二沟槽中形成低电阻金属层。
-
公开(公告)号：US20180226251A1
公开(公告)日：2018-08-09
申请号：US15885827
申请日：2018-02-01
Inventor： Kai-Ping Chen , Kuei-Hsuan Yu , Chiu-Hsien Yeh , Li-Wei Feng
IPC: H01L21/033 , H01L21/02 , H01L21/311 , H01L21/027
CPC classification number: H01L21/0338 , H01L21/02118 , H01L21/02356 , H01L21/0273 , H01L21/0332 , H01L21/0337 , H01L21/31144 , H01L27/10814 , H01L27/10823 , H01L27/10852
Abstract: A method for forming patterns of semiconductor device is provided in the present invention, with steps of filling up first self-assembly material in first openings in a dielectric layer, phase-separating the first self-assembly material to form a first portion and a second portion surrounding the first portion, removing the first portion and performing a first etch process to form a first mask pattern in a mask layer, forming a second dielectric layer and repeating the above steps to form a second mask pattern in the mask layer, wherein the second mask pattern is aligned with the first mask pattern to form a common mask pattern.
-
公开(公告)号：US10157744B2
公开(公告)日：2018-12-18
申请号：US15885827
申请日：2018-02-01
Inventor： Kai-Ping Chen , Kuei-Hsuan Yu , Chiu-Hsien Yeh , Li-Wei Feng
IPC: H01L21/311 , H01L21/033 , H01L21/02 , H01L21/027 , H01L27/108
Abstract: A method for forming patterns of semiconductor device is provided in the present invention, with steps of filling up first self-assembly material in first openings in a dielectric layer, phase-separating the first self-assembly material to form a first portion and a second portion surrounding the first portion, removing the first portion and performing a first etch process to form a first mask pattern in a mask layer, forming a second dielectric layer and repeating the above steps to form a second mask pattern in the mask layer, wherein the second mask pattern is aligned with the first mask pattern to form a common mask pattern.
-
公开(公告)号：US09899491B2
公开(公告)日：2018-02-20
申请号：US15182620
申请日：2016-06-15
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Po-Wen Su , Zhen Wu , Hsiao-Pang Chou , Chiu-Hsien Yeh , Shui-Yen Lu , Jian-Wei Chen
IPC: H01L29/51 , H01L21/82 , H01L27/088 , H01L29/66 , H01L29/40 , H01L21/8234 , H01L29/423
CPC classification number: H01L29/512 , H01L21/82345 , H01L21/823462 , H01L27/088 , H01L29/401 , H01L29/4236 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L29/66553 , H01L29/78
Abstract: A semiconductor device and a method of forming the same, the semiconductor device include a substrate, and a first gate structure and a second gate structure disposed on the substrate. The first gate structure includes a barrier layer, a first work function layer, a second work function layer and a conductive layer stacked one over another on the substrate. The second gate structure includes the barrier layer, a portion of the first work function layer and the conductive layer stacked one over another on the substrate, wherein the portion of the first work function layer has a smaller thickness than a thickness of the first work function layer.
-
-
-
-
-
-
-
-
-
Search Results
17
records
(took 0.016 seconds)
