公开(公告)号：US20240321973A1

公开(公告)日：2024-09-26

申请号：US18138728

申请日：2023-04-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Hua Yang ,  Chih-Chien CHANG ,  Shen-De WANG ,  JIANJUN YANG ,  Wei Ta ,  Yuan-Hsiang Chang

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H10B41/35

CPC classification number: H01L29/404 ,  H01L29/401 ,  H01L29/66681 ,  H01L29/66825 ,  H01L29/7816 ,  H10B41/35

Abstract: A power metal-oxide-semiconductor structure includes a semiconductor substrate, a gate electrode disposed above the semiconductor substrate, a field plate, and an electrically conductive pattern. The gate electrode and the field plate are disposed above the semiconductor substrate, the electrically conductive pattern is disposed between the field plate and the semiconductor substrate in a vertical direction, and the field plate and the electrically conductive pattern are located at the same side of the gate electrode in a horizontal direction. A manufacturing method of a power metal-oxide-semiconductor structure includes the following steps. The electrically conductive pattern and the field plate are formed above a first region of the semiconductor substrate. Subsequently, the gate electrode is formed above the first region of the semiconductor substrate.

公开(公告)号：US20190139971A1

公开(公告)日：2019-05-09

申请号：US15808019

申请日：2017-11-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chang LIU ,  Zhen CHEN ,  Shen-De WANG ,  Chuan SUN ,  Wei TA ,  Wang XIANG

IPC: H01L27/11531 ,  H01L27/11521 ,  H01L29/423 ,  H01L29/788 ,  H01L21/28 ,  H01L21/3215 ,  H01L21/266 ,  H01L29/66

Abstract: A method for forming a semiconductor device is provided, including providing a substrate having a first area comprising first semiconductor structures and a second area, wherein one of the first semiconductor structures comprises a memory gate made of a first polysilicon layer, and a second semiconductor structure comprises a second polysilicon layer disposed within the second area on the substrate; forming an organic material layer on the first semiconductor structures within the first area and on the second polysilicon layer within the second area; and patterning the organic material layer to form a patterned organic material layer, and the organic material layer exposing the memory gates of the first semiconductor structures, wherein a first pre-determined region and a second pre-determined region at the substrate are covered by the patterned organic material layer.