Abstract:
A manufacturing method for a semiconductor device includes: providing a substrate including a first gate structure disposed thereon, wherein the first gate structure includes a first gate electrode and a first hard mask covers the first gate electrode. A first oxide spacer and a silicon carbon nitride spacer are formed in sequence to surround the first gate electrode. A thermal treatment is performed to form a silicon oxycarbonitride layer between the first oxide spacer and the silicon carbon nitride spacer. Then, a second oxide spacer, a third oxide spacer, and a first silicon nitride spacer are formed on the silicon carbon nitride spacer in sequence. The first hard mask and the first silicon nitride spacer are removed. Finally, the third oxide spacer, the second oxide spacer, and silicon carbon nitride spacer are removed entirely to expose the silicon oxycarbonitride layer.
Abstract:
A semiconductor structure and a method for forming the same are provided. The method includes following steps. A gate electrode layer is formed on a substrate. A spacer structure is formed on a sidewall of the gate electrode layer. A dielectric cap film is formed to cover the gate electrode layer and the spacer structure. A source/drain implantation is performed to the substrate with the dielectric cap film exposed to a condition of the source/drain implantation.
Abstract:
A semiconductor structure and a method for forming the same are provided. The method includes following steps. A gate electrode layer is formed on a substrate. A spacer structure is formed on a sidewall of the gate electrode layer. A dielectric cap film is formed to cover the gate electrode layer and the spacer structure. A source/drain implantation is performed to the substrate with the dielectric cap film exposed to a condition of the source/drain implantation.
Abstract:
A method for fabricating a semiconductor device is described. A semiconductor substrate is provided, wherein the substrate has a first area and a second area. A first gate structure and a second gate structure are formed over the substrate in the first area and the substrate in the second area, respectively. A first spacer is framed on the sidewall of each gate structure. At least one etching process including at least one wet etching process is performed. The first spacer is removed. A second spacer is formed on the sidewall of each gate structure. A mask layer is formed in the second area. Ion implantation is formed using the mask layer, the first gate structure and the second spacer as a mask to form S/D extensions in the substrate beside the first gate structure in the first area. The mask layer is then removed.