公开(公告)号：US12230509B2

公开(公告)日：2025-02-18

申请号：US17029021

申请日：2020-09-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming Thai Chai ,  Meng Xie ,  Wenbo Ding

IPC: H01L21/324 ,  H01L21/02 ,  H01L21/285 ,  H01L21/762 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a gate structure on a substrate; forming a source/drain region adjacent to the gate structure; performing a first cleaning process; performing a first rapid thermal anneal (RTA) process to remove oxygen cluster in the substrate; forming a metal layer on the source/drain region; and performing a second RTA process to transform the metal layer into a silicide layer.

公开(公告)号：US10916634B2

公开(公告)日：2021-02-09

申请号：US16417542

申请日：2019-05-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei Xu ,  Wenbo Ding ,  Yu-Yang Chen ,  Wang Xiang

IPC: H01L21/28 ,  H01L27/11563 ,  H01L21/033

Abstract: A method of fabricating a semiconductor device includes forming a memory gate and a hard mask layer on the memory gate, forming a select gate on a sidewall of the memory gate and the hard mask layer, performing a selective oxidation process to form an oxide layer on the hard mask layer and the select gate, wherein a portion of the oxide layer on the select gate is thicker than a portion of the oxide layer on the hard mask layer, and removing the oxide layer on the hard mask layer and the hard mask layer to expose a top surface of the memory gate.

公开(公告)号：US09780101B1

公开(公告)日：2017-10-03

申请号：US15361065

申请日：2016-11-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Sheng Zhang ,  Wenbo Ding ,  Xiaofei Han ,  Chien-Kee Pang ,  Yu-Yang Chen ,  Jubao Zhang

IPC: H01L21/8238 ,  H01L21/336 ,  H01L29/788 ,  H01L27/11521 ,  H01L29/66

CPC classification number: H01L27/11521 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

Abstract: The present invention provides a flash cell structure and a method of fabricating the same. The flash cell structure includes a semiconductor substrate, a stacked gate structure disposed on the semiconductor substrate, a first doped region disposed in the semiconductor substrate at a side of the stacked gate structure, a first dielectric layer, a second dielectric layer, and an erase gate. The stacked gate structure includes a floating gate insulated from the semiconductor substrate and a control gate disposed on the floating gate and insulated from the floating gate. The first dielectric layer is disposed on a sidewall of the floating gate. The second dielectric layer is disposed on the first doped region. A thickness of the first dielectric layer is less than a thickness of the second dielectric layer.