公开(公告)号：US20230025163A1

公开(公告)日：2023-01-26

申请号：US17404939

申请日：2021-08-17

Applicant: United Microelectronics Corp.

Inventor： Wen Wen Gong ,  Xiaofei Han ,  Chow Yee Lim ,  Hong Liao ,  Jun Qian

IPC: H01L21/308 ,  H01L27/11556

Abstract: A method of manufacturing a semiconductor structure including the following steps is provided. A substrate is provided. The substrate has a first region and a second region. A stacked structure is formed on the substrate in the first region. The stacked structure includes a first dielectric layer, a charge storage layer, a second dielectric layer, a first conductive layer, and a first hard mask layer. A dielectric material layer is formed on the substrate in the second region. A second conductive layer is formed on the dielectric material layer in the second region. A first patterned photoresist layer is formed. The first hard mask layer exposed by the first patterned photoresist layer and a portion of the dielectric material layer exposed by the first patterned photoresist layer are removed by using the first patterned photoresist layer as a mask.

公开(公告)号：US10147806B1

公开(公告)日：2018-12-04

申请号：US15602114

申请日：2017-05-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Bin Tang ,  Jubao Zhang ,  Xiaofei Han ,  Chao Jiang ,  Hong Liao

IPC: H01L21/283 ,  H01L21/762 ,  H01L27/11531 ,  H01L29/788 ,  H01L29/66 ,  H01L27/11521 ,  H01L21/8234

Abstract: A method of fabricating a floating gate includes providing a substrate divided into a cell region and a logic region. A silicon oxide layer and a silicon nitride layer cover the cell region and the logic region. Numerous STIs are formed in the silicon nitride layer, the silicon oxide layer, and the substrate. Later, the silicon nitride layer within the cell region is removed to form one recess between the adjacent STIs within the cell region while the silicon nitride layer within the logic region remains. Subsequently, a conductive layer is formed to fill the recess. The conductive layer is thinned to form a floating gate.

公开(公告)号：US09780101B1

公开(公告)日：2017-10-03

申请号：US15361065

申请日：2016-11-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Sheng Zhang ,  Wenbo Ding ,  Xiaofei Han ,  Chien-Kee Pang ,  Yu-Yang Chen ,  Jubao Zhang

IPC: H01L21/8238 ,  H01L21/336 ,  H01L29/788 ,  H01L27/11521 ,  H01L29/66

CPC classification number: H01L27/11521 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

Abstract: The present invention provides a flash cell structure and a method of fabricating the same. The flash cell structure includes a semiconductor substrate, a stacked gate structure disposed on the semiconductor substrate, a first doped region disposed in the semiconductor substrate at a side of the stacked gate structure, a first dielectric layer, a second dielectric layer, and an erase gate. The stacked gate structure includes a floating gate insulated from the semiconductor substrate and a control gate disposed on the floating gate and insulated from the floating gate. The first dielectric layer is disposed on a sidewall of the floating gate. The second dielectric layer is disposed on the first doped region. A thickness of the first dielectric layer is less than a thickness of the second dielectric layer.