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    System and method for analog to digital conversion
    1.
    发明授权
    System and method for analog to digital conversion 有权
    用于模数转换的系统和方法

    公开(公告)号：US09362935B2

    公开(公告)日：2016-06-07

    申请号：US14421534

    申请日：2013-08-13

    Applicant: University of South Australia

    Inventor： Ying Chen ,  Andre Pollok ,  David Victor Lawrie Haley ,  Linda Mary Davis ,  Mark Damian McDonnell

    IPC: H03M1/80 ,  H03M1/08 ,  H03M1/18 ,  H03M1/36

    CPC classification number: H03M1/0854 ,  H03M1/188 ,  H03M1/361

    Abstract: Parallel analog to digital converted (ADC) architectures that can be used to replace single path ADC architectures. The parallel ADC architecture can comprise N branches and one ADC per branch. These ADCs can be identical. However each branch can have a different path adjustments applied to the ADC. The path adjustments can be biases and/or gains and each ADC receives a different combination of biases and/or gain to generate multiple adjusted input signals. These are then combined to generate a quantized output signal. Using these parallel architectures a range of weighting and offset combining schemes can be employed to achieve improvements in signal to noise ratio and to reduce the impact of clipping as compared to a single path ADC architecture.

    Abstract translation: 并行模数转换（ADC）架构，可用于替代单路ADC架构。 并行ADC架构可以包括每个分支的N个分支和一个ADC。 这些ADC可以相同。 然而，每个分支可以具有应用于ADC的不同路径调整。 路径调整可以是偏置和/或增益，并且每个ADC接收偏差和/或增益的不同组合以产生多个经调整的输入信号。 然后将它们组合以产生量化的输出信号。 使用这些并行架构，可以采用一系列加权和偏移组合方案来实现信噪比的提高，并减少与单路ADC结构相比的限幅的影响。

    Enhanced Automatic identification System
    2.
    发明申请
    Enhanced Automatic identification System 审中-公开
    增强自动识别系统

    公开(公告)号：US20160277145A1

    公开(公告)日：2016-09-22

    申请号：US14913775

    申请日：2014-08-22

    Applicant: UNIVERSITY OF SOUTH AUSTRALIA

    Inventor： Alexander James Grant ,  Andre Pollok ,  Gottfried Lechner ,  David Victor Lawrie Haley ,  Robert George McKilliam ,  Ingmar Rudiger Land ,  Marc Pierre Denis Lavenant

    IPC: H04L1/00

    CPC classification number: H04L1/0041 ,  H03M5/145 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/23 ,  H03M13/2957 ,  H03M13/31 ,  H03M13/6325 ,  H03M13/6356 ,  H04L1/00 ,  H04L1/0045 ,  H04L1/0061 ,  H04L1/0071

    Abstract: The invention relates to method and apparatus for improving the performance of communication systems using Run Length Limited (RLL) messages such as the existing Automatic Identification System (AIS). A binary data sequence is Forward Error Correction (FEC) coded and then the sequence is compensated, for example by bit-erasure, so that either bit-stuffing is not required, or a bit stuffer will not be activated to ensure that the coded sequence meets the RLL requirement. Various embodiments are described to handle different architectures or input points for the FEC encoder and bit erasure module. The bit erasure module may also add dummy bits to ensure a RLL compliant CRC or to selectively add bits to a reserve buffer to compensate for later bit stuffing in a header. Additional RLL training sequences may also be added to assist in, receiver acquisition.

    Abstract translation: 本发明涉及使用诸如现有自动识别系统（AIS）的运行长度限制（RLL）消息来改善通信系统性能的方法和装置。 二进制数据序列是前向纠错（FEC）编码的，然后例如通过比特擦除来补偿序列，使得不需要任何一个比特填充，或者一个填充填充器将不被激活以确保编码序列 符合RLL要求。 描述了各种实施例来处理用于FEC编码器和位擦除模块的不同架构或输入点。 位擦除模块还可以添加虚拟位以确保符合RLL的CRC或者选择性地将位添加到保留缓冲器以补偿在标题中稍后的位填充。 还可以添加额外的RLL训练序列以辅助接收器采集。

    System and Method for Analog to Digital Conversion
    6.
    发明申请
    System and Method for Analog to Digital Conversion 有权
    用于模数转换的系统和方法

    公开(公告)号：US20150188556A1

    公开(公告)日：2015-07-02

    申请号：US14421534

    申请日：2013-08-13

    Applicant: University of South Australia

    Inventor： Ying Chen ,  Andre Pollok ,  David Victor Lawrie Haley ,  Linda Mary Davis ,  Mark Damian McDonnell

    IPC: H03M1/08 ,  H03M1/36

    CPC classification number: H03M1/0854 ,  H03M1/188 ,  H03M1/361

    Abstract: Parallel analog to digital converted (ADC) architectures that can be used to replace single path ADC architectures. The parallel ADC architecture can comprise N branches and one ADC per branch. These ADCs can be identical. However each branch can have a different path adjustments applied to the ADC. The path adjustments can be biases and/or gains and each ADC receives a different combination of biases and/or gain to generate multiple adjusted input signals. These are then combined to generate a quantised output signal. Using these parallel architectures a range of weighting and offset combining schemes can be employed to achieve improvements in signal to noise ratio and to reduce the impact of clipping as compared to a single path ADC architecture.

    Abstract translation: 并行模数转换（ADC）架构，可用于替代单路ADC架构。 并行ADC架构可以包括每个分支的N个分支和一个ADC。 这些ADC可以相同。 然而，每个分支可以具有应用于ADC的不同路径调整。 路径调整可以是偏置和/或增益，并且每个ADC接收偏差和/或增益的不同组合以产生多个经调整的输入信号。 然后将它们组合以产生量化的输出信号。 使用这些并行架构，可以采用一系列加权和偏移组合方案来实现信噪比的提高，并减少与单路ADC结构相比的限幅的影响。

    A Multiuser Communications System
    10.
    发明申请
    A Multiuser Communications System 审中-公开
    多用户通信系统

    公开(公告)号：US20160204852A1

    公开(公告)日：2016-07-14

    申请号：US14913339

    申请日：2014-08-21

    Applicant: UNIVERSITY OF SOUTH AUSTRALIA

    Inventor： Alexander James Grant ,  Gottfried Lechner ,  Andre Pollok ,  Robert George McKilliam ,  Ingmar Rudiger Land ,  David Victor Lawrie Haley ,  William George Cowley ,  Linda Mary Davis ,  Sorin Adrian Barbulescu ,  John Lawrence Buetefuer ,  Marc Pierre Denis Lavenant

    IPC: H04B7/185 ,  H04W72/04 ,  H04W72/08

    CPC classification number: H04B7/18539 ,  H04B1/7107 ,  H04W72/0446 ,  H04W72/082 ,  H04W88/02

    Abstract: A multiuser communication system comprises multiple transmitters and a multiuser receiver that detects multiple transmissions via iterative soft interference cancellation. An initial acquisition module and single user decoder module are also described. The multiuser receiver acquires and subtracts known users in the residual signal before acquiring new users in the residual signal, which is performed iteratively until no new users are detected or a stopping criterion is met. To aid receiver acquisition, the transmitters insert discrete tones into the transmitted signals. These allow the multiuser receiver to obtain initial estimates of the frequency, time, gain, and/or phase offset for each user. To improve the quality of cancellation the receiver refines estimates of gain, time, frequency and phase offsets for each user after each iteration, and calculates time varying SINR estimates for each user. The multiuser receiver may be satellite based, may be a distributed receiver, or process users in parallel.

    Abstract translation: 多用户通信系统包括多个发射机和通过迭代软干扰消除来检测多个传输的多用户接收机。 还描述了初始采集模块和单用户解码器模块。 多用户接收机在获取剩余信号中的新用户之前，对残留信号中的已知用户进行迭代，获取并减去已知用户，直到不检测到新的用户或满足停止标准为止。 为了帮助接收机采集，发射机将离散音调插入发射信号。 这些允许多用户接收机获得每个用户的频率，时间，增益和/或相位偏移的初始估计。 为了提高取消的质量，接收机在每次迭代之后对每个用户的增益，时间，频率和相位偏移的估计进行精细化，并计算每个用户的时变SINR估计。 多用户接收机可以是基于卫星的，可以是分布式接收机，或并行处理用户。

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