公开(公告)号：US20230225139A1

公开(公告)日：2023-07-13

申请号：US18122718

申请日：2023-03-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhaoyao Zhan ,  QIANWEI DING ,  XIAOHONG JIANG ,  CHING HWA TEY

IPC: H10K39/32 ,  H10K85/50

CPC classification number: H10K39/32 ,  H10K85/50

Abstract: The present invention provides an image sensor, the image sensor includes a substrate, a first circuit layer on the substrate, at least one nanowire photodiode located on the first circuit layer and electrically connected with the first circuit layer, wherein the nanowire photodiode comprises a lower material layer and an upper material layer, and a P-N junction or a Schottky junction is arranged between the lower material layer and the upper material layer, wherein the lower material layer comprises a perovskite material, and a precursor layer located under the lower material layer, wherein the precursor layer comprises different metal elements as the lower material layer

公开(公告)号：US20210167170A1

公开(公告)日：2021-06-03

申请号：US16700504

申请日：2019-12-02

Applicant: United Microelectronics Corp

Inventor： Zhaoyao Zhan

IPC: H01L29/06 ,  H01L21/265 ,  H01L29/66 ,  H01L21/306 ,  H01L21/762 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423

Abstract: A method of manufacturing a semiconductor device including following steps is provided. A substrate is provided. An ion implantation process is performed on the substrate to form doped material layers at different depth positions of the substrate and to define at least one nanowire layer. The at least one nanowire layer and the doped material layers are alternately stacked. A patterning process is performed on the at least one nanowire layer and the doped material layers to form at least one nanowire and doped layers. The at least one nanowire and the doped layers are alternately stacked to form a stack structure. A dummy gate structure spanning over the stack structure is formed. Spacers located on sidewalls of the dummy gate structure is formed. The dummy gate structure is removed to expose the at least one nanowire and the doped layers. The exposed doped layers are removed to form openings.

公开(公告)号：US12080734B2

公开(公告)日：2024-09-03

申请号：US17984243

申请日：2022-11-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhaoyao Zhan ,  Qianwei Ding ,  Xiaohong Jiang ,  Ching Hwa Tey

IPC: H01L27/146

CPC classification number: H01L27/1461 ,  H01L27/14623

Abstract: A method for forming a photosensitive device includes the steps of providing an integrated circuit structure having a first pad and a second pad exposed from a surface of the integrated circuit structure, forming a first material layer on the surface of the integrated circuit structure, patterning the first material layer to expose the second pad, forming a second material layer on the first material layer and covering the second pad, and patterning the second material.

公开(公告)号：US20230076390A1

公开(公告)日：2023-03-09

申请号：US17984261

申请日：2022-11-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhaoyao Zhan ,  QIANWEI DING ,  XIAOHONG JIANG ,  CHING HWA TEY

IPC: H01L27/146

Abstract: A photosensitive device is disclosed, including an integrated circuit structure, a first pad and a second pad exposed from a surface of the integrated circuit structure, a first material layer disposed on the surface of the integrated circuit structure and covering the first pad, and a second material layer disposed on the first material layer and covering the second pad. The first material layer and the second material layer form a heterojunction photodiode.

公开(公告)号：US20240395834A1

公开(公告)日：2024-11-28

申请号：US18795147

申请日：2024-08-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhaoyao Zhan ,  Qianwei DING ,  Xiaohong JIANG ,  Ching Hwa TEY

IPC: H01L27/146

Abstract: A photosensitive device includes an integrated circuit structure and a plurality of photodiodes disposed on the integrated circuit structure. The photodiodes respectively includes a first material layer and a second material layer overlapping on the first material layer and extending beyond the first material layer to directly contact a surface of the integrated circuit structure. The first material layer and the second material layer are made of two-dimensional semiconductor materials.

公开(公告)号：US20220165895A1

公开(公告)日：2022-05-26

申请号：US17137300

申请日：2020-12-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhaoyao Zhan ,  QIANWEI DING ,  XIAOHONG JIANG ,  CHING HWA TEY

IPC: H01L31/032 ,  H01L27/146 ,  H01L31/0352 ,  H01L31/028

Abstract: The invention provides an image sensor, the image sensor includes a substrate, a first circuit layer located on the substrate, and at least one nanowire photodiode located on the first circuit layer and electrically connected to the first circuit layer, the nanowire photodiode comprises a lower material layer and an upper material layer with a P-N junction between the lower material layer and the upper material layer, the lower material layer includes perovskite material.

公开(公告)号：US11189691B2

公开(公告)日：2021-11-30

申请号：US16700504

申请日：2019-12-02

Applicant: United Microelectronics Corp.

Inventor： Zhaoyao Zhan

IPC: H01L29/06 ,  H01L21/265 ,  H01L29/66 ,  H01L21/306 ,  H01L21/762 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08

Abstract: A method of manufacturing a semiconductor device including following steps is provided. A substrate is provided. An ion implantation process is performed on the substrate to form doped material layers at different depth positions of the substrate and to define at least one nanowire layer. The at least one nanowire layer and the doped material layers are alternately stacked. A patterning process is performed on the at least one nanowire layer and the doped material layers to form at least one nanowire and doped layers. The at least one nanowire and the doped layers are alternately stacked to form a stack structure. A dummy gate structure spanning over the stack structure is formed. Spacers located on sidewalls of the dummy gate structure is formed. The dummy gate structure is removed to expose the at least one nanowire and the doped layers. The exposed doped layers are removed to form openings.

公开(公告)号：US11101361B1

公开(公告)日：2021-08-24

申请号：US16886744

申请日：2020-05-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhaoyao Zhan ,  Qianwei Ding ,  Xiaohong Jiang ,  Ching Hwa Tey

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L21/762 ,  H01L29/66 ,  H01L29/76 ,  H01L29/16 ,  H01L29/24

Abstract: A GAA transistor includes a semiconductor substrate. A first shallow trench isolation (STI) is embedded in the semiconductor substrate. A top surface of the first STI is lower than a top surface of the semiconductor substrate. A nanowire crosses the first STI and is disposed on the first STI. A gate structure contacts and wraps around the nanowire. A source electrode contacts a first end of the nanowire. A drain electrode contacts a second end of the nanowire.

公开(公告)号：US20250031585A1

公开(公告)日：2025-01-23

申请号：US18447317

申请日：2023-08-10

Applicant: United Microelectronics Corp.

Inventor： Zhaoyao Zhan ,  Jian Shi ,  Xiaohong Jiang ,  Ching-Hwa Tey

IPC: H10N70/00 ,  H10B63/00

Abstract: A resistive random access memory includes a first electrode, a second electrode, a dielectric layer, a protection layer, and at least one switching layer. The dielectric layer is formed on the first electrode. The dielectric layer has an opening exposing a portion of the first electrode. The protection layer is disposed on sidewalls of the opening. The switching layer is disposed on the exposed portion of the first electrode and exposes a portion of sidewalls of the protection layer. The second electrode is at least one conductive layer and is disposed on the switching layer in the opening.

公开(公告)号：US20250022905A1

公开(公告)日：2025-01-16

申请号：US18900947

申请日：2024-09-30

Applicant: United Microelectronics Corp.

Inventor： Zhaoyao Zhan ,  Jing Feng ,  Qianwei Ding ,  Xiaohong Jiang ,  Ching-Hwa Tey

IPC: H01L27/146

Abstract: An image sensor structure including a substrate, a nanowire structure, a first conductive line, a second conductive line, and a third conductive line is provided. The nanowire structure includes a first doped layer, a second doped layer, a third doped layer, and a fourth doped layer sequentially stacked on the substrate. The first doped layer and the third doped layer have a first conductive type. The second doped layer and the fourth doped layer have a second conductive type. The first conductive line is connected to a sidewall of the second doped layer. The second conductive line is connected to a sidewall of the third doped layer. The third conductive line is connected to the fourth doped layer.