公开(公告)号：US20200212030A1

公开(公告)日：2020-07-02

申请号：US16255786

申请日：2019-01-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Liang Chu ,  Chih-Hsien Tang ,  Yu-Ruei Chen ,  Ya-Huei Tsai ,  Rai-Min Huang ,  Chueh-Fei Tai

IPC: H01L27/02 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  G03F1/36

Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes: a first magnetic tunneling junction (MTJ) pattern on a substrate; a second MTJ pattern adjacent to the first MTJ pattern; and a first metal interconnection pattern between the first MTJ pattern and the second MTJ pattern, wherein the first MTJ pattern, the first metal interconnection pattern, and the second MTJ pattern comprise a staggered arrangement.

公开(公告)号：US10714466B1

公开(公告)日：2020-07-14

申请号：US16255786

申请日：2019-01-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chung-Liang Chu ,  Chih-Hsien Tang ,  Yu-Ruei Chen ,  Ya-Huei Tsai ,  Rai-Min Huang ,  Chueh-Fei Tai

IPC: H01L27/22 ,  H01L27/02 ,  G03F1/36 ,  H01L43/12 ,  H01L43/02

Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes: a first magnetic tunneling junction (MTJ) pattern on a substrate; a second MTJ pattern adjacent to the first MTJ pattern; and a first metal interconnection pattern between the first MTJ pattern and the second MTJ pattern, wherein the first MTJ pattern, the first metal interconnection pattern, and the second MTJ pattern comprise a staggered arrangement.

公开(公告)号：US20190221639A1

公开(公告)日：2019-07-18

申请号：US15870267

申请日：2018-01-12

Applicant: United Microelectronics Corp.

Inventor： Kuan-Hao Tseng ,  Yu-Hsiang Lin ,  Shih-Hung Tsai ,  Po-Kuang Hsieh ,  Yu-Ting Tseng ,  Chueh-Fei Tai ,  Cheng-Ping Kuo

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/308 ,  H01L29/08 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/10 ,  H01L21/306 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabrication a nanosheet device includes providing forming a stacked layer on a substrate, having first material layers and second material layers in different materials, alternatingly stacked up. The stacked layer is patterned to a stacked fin. A dummy stack is formed on the stacked fin. An etching back process is performed with the dummy stack with spacers to etch the stacked fin and expose the substrate. Laterally etches the first material layers and the second material layers, to have indent portions. Inner spacers fill the indent portions. A first/second source/drain layer is formed on the substrate at both sides of the dummy stack. Etching process is performed to remove the dummy gate of the dummy stack and the selected one of the first material layers and the second material layers between the inner spacers. Metal layer fills between the spacers and the inner spacers.

公开(公告)号：US10707135B2

公开(公告)日：2020-07-07

申请号：US15806277

申请日：2017-11-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Hao Tseng ,  Chien-Ting Lin ,  Shih-Hung Tsai ,  Po-Kuang Hsieh ,  Yu-Ting Tseng ,  Chueh-Fei Tai ,  Cheng-Ping Kuo

IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/308 ,  H01L21/306 ,  H01L21/02 ,  H01L27/092 ,  H01L29/165 ,  H01L21/3065 ,  H01L29/66 ,  H01L29/167 ,  H01L21/762 ,  H01L21/266 ,  H01L21/265

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first well in the substrate on the first region and a second well in the substrate on the second region; removing part of the first well to form a first recess; and forming a first epitaxial layer in the first recess.

公开(公告)号：US20190131183A1

公开(公告)日：2019-05-02

申请号：US15806277

申请日：2017-11-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Hao Tseng ,  Chien-Ting Lin ,  Shih-Hung Tsai ,  Po-Kuang Hsieh ,  Yu-Ting Tseng ,  Chueh-Fei Tai ,  Cheng-Ping Kuo

IPC: H01L21/8238 ,  H01L21/308 ,  H01L21/306 ,  H01L21/762 ,  H01L21/02 ,  H01L27/092 ,  H01L29/165 ,  H01L21/3065

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first well in the substrate on the first region and a second well in the substrate on the second region; removing part of the first well to form a first recess; and forming a first epitaxial layer in the first recess.