公开(公告)号：US20240334710A1

公开(公告)日：2024-10-03

申请号：US18740496

申请日：2024-06-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Hung Tsai ,  Hon-Huei Liu ,  Chun-Hsien Lin

IPC: H10B53/30 ,  H01L27/12 ,  H01L27/13

CPC classification number: H10B53/30 ,  H01L27/1207 ,  H01L27/13

Abstract: A method for fabricating a semiconductor device includes the steps of forming a metal-oxide semiconductor (MOS) transistor on a substrate, forming an interlayer dielectric (ILD) layer on the MOS transistor, forming a ferroelectric field effect transistor (FeFET) on the ILD layer, and forming a ferroelectric random access memory (FeRAM) on the ILD layer. The formation of the FeFET further includes first forming a semiconductor layer on the ILD layer, forming a gate structure on the semiconductor layer, and then forming a source/drain region adjacent to the gate structure.

公开(公告)号：US20240072097A1

公开(公告)日：2024-02-29

申请号：US17953309

申请日：2022-09-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Shih-Hung Tsai

IPC: H01L27/146

CPC classification number: H01L27/14687 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14692

Abstract: A method for fabricating a semiconductor device includes the steps of providing a first wafer and a second wafer as the first wafer includes a device wafer and the second wafer includes a blanket wafer, bonding the first wafer and the second wafer, performing a thermal treatment process to separate the second wafer into a first portion and a second portion, and then planarizing the first portion.

公开(公告)号：US11735646B2

公开(公告)日：2023-08-22

申请号：US17090902

申请日：2020-11-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chang Lin ,  Bo-Han Huang ,  Chih-Chung Chen ,  Chun-Hsien Lin ,  Shih-Hung Tsai ,  Po-Kuang Hsieh

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/51

CPC classification number: H01L29/66795 ,  H01L21/02052 ,  H01L21/02054 ,  H01L29/517 ,  H01L29/7851

Abstract: A method for fabricating semiconductor device includes the steps of: forming fin-shaped structures on a substrate; using isopropyl alcohol (IPA) to perform a rinse process; performing a baking process; and forming a gate oxide layer on the fin-shaped structures. Preferably, a duration of the rinse process is between 15 seconds to 60 seconds, a temperature of the baking process is between 50° C. to 100° C., and a duration of the baking process is between 5 seconds to 120 seconds.

公开(公告)号：US20230009805A1

公开(公告)日：2023-01-12

申请号：US17393384

申请日：2021-08-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Hung Tsai ,  Hon-Huei Liu ,  Chun-Hsien Lin

IPC: H03H9/05 ,  H03H3/08 ,  H03H9/02

Abstract: A method for fabricating a surface acoustic wave (SAW) device includes the steps of forming a first dielectric layer on a substrate, forming a piezoelectric layer on the first dielectric layer, forming a second dielectric layer on the piezoelectric layer, performing a photo-etching process to remove the second dielectric layer for forming a recess in the second dielectric layer, forming a metal layer in the recess, and then performing a planarizing process to remove the metal layer for forming an electrode in the recess.

公开(公告)号：US11387148B2

公开(公告)日：2022-07-12

申请号：US16872395

申请日：2020-05-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chao-Hung Lin ,  Hon-Huei Liu ,  Shih-Fang Hong ,  Jyh-Shyang Jenq

IPC: H01L21/8238 ,  H01L21/225 ,  H01L21/324 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, wherein each of the first fin-shaped structure and the second fin-shaped structure comprises a top portion and a bottom portion; a first doped layer around the bottom portion of the first fin-shaped structure; a second doped layer around the bottom portion of the second fin-shaped structure; a first liner on the first doped layer; and a second liner on the second doped layer.

公开(公告)号：US09754938B1

公开(公告)日：2017-09-05

申请号：US15187800

申请日：2016-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Tong-Jyun Huang ,  Shih-Hung Tsai ,  Jia-Rong Wu ,  Tien-Chen Chan ,  Yu-Shu Lin ,  Jyh-Shyang Jenq

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/31144 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/0649 ,  H01L29/66545

Abstract: A semiconductor device includes a substrate, fin-shaped structures, a protection layer, epitaxial layers, and a gate electrode. The fin-shaped structures are disposed in a first region and a second region of the substrate. The protection layer conformally covers the surface of the substrate and the sidewalls of fin-shaped structures. The epitaxial layers respectively conformally and directly cover the fin-shaped structures in the first region. The gate electrode covers the fin-shaped structures in the second region, and the protection layer is disposed between the gate electrode and the fin-shaped structures.

公开(公告)号：US20170047426A1

公开(公告)日：2017-02-16

申请号：US15335418

申请日：2016-10-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ting Lin ,  Shih-Hung Tsai

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/06 ,  H01L27/092 ,  H01L21/762 ,  H01L29/08

CPC classification number: H01L29/66598 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7851

Abstract: A complementary metal oxide semiconductor field-effect transistor (MOSFET) includes a substrate, a first MOSFET and a second MOSFET. The first MOSFET is disposed on the substrate within a first transistor region and the second MOSFET is disposed on the substrate within a second transistor region. The first MOSFET includes a first fin structure, two first lightly-doped regions, two first doped regions and a first gate structure. The first fin structure includes a first body portion and two first epitaxial portions, wherein each of the first epitaxial portions is disposed on each side of the first body portion. A first vertical interface is between the first body portion and each of the first epitaxial portions so that the first-lightly doped region is able to be uniformly distributed on an entire surface of each first vertical interface.

Abstract translation: 互补金属氧化物半导体场效应晶体管（MOSFET）包括衬底，第一MOSFET和第二MOSFET。 第一MOSFET设置在第一晶体管区域内的衬底上，并且第二MOSFET设置在第二晶体管区域内的衬底上。 第一MOSFET包括第一鳍结构，两个第一轻掺杂区，两个第一掺杂区和第一栅结构。 第一翅片结构包括第一主体部分和两个第一外延部分，其中每个第一外延部分设置在第一主体部分的每一侧上。 第一垂直接口位于第一主体部分和第一外延部分之间，使得第一轻掺杂区域能够均匀分布在每个第一垂直界面的整个表面上。

公开(公告)号：US09553026B1

公开(公告)日：2017-01-24

申请号：US14960447

申请日：2015-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chao-Hung Lin ,  Chien-Ting Lin ,  Li-Chiang Chen ,  Jyh-Shyang Jenq

IPC: H01L21/30 ,  H01L21/8234 ,  H01L27/11 ,  H01L27/088 ,  H01L21/308 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/3086 ,  H01L27/0886 ,  H01L27/1104 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a first mandrel, a second mandrel, a third mandrel, and a fourth mandrel are formed on the substrate. Preferably, the first mandrel and the second mandrel include a first gap therebetween, the second mandrel and the third mandrel include a second gap therebetween, and the third mandrel and the fourth mandrel include a third gap therebetween, in which the first gap is equivalent to the third gap but different from the second gap. Next, spacers are formed adjacent to the first mandrel, the second mandrel, the third mandrel, and the fourth mandrel, and the spacers in the first gap and the third gap are removed.

Abstract translation: 公开了半导体器件的制造方法。 首先，设置基板，在基板上形成第一芯轴，第二心轴，第三心轴，第四心轴。 优选地，第一心轴和第二心轴包括其间的第一间隙，第二心轴和第三心轴在其间包括第二间隙，并且第三心轴和第四心轴在其间包括第三间隙，其中第一间隙等于 第三个差距，但与第二个差距不同。 接下来，在第一心轴，第二心轴，第三心轴和第四心轴附近形成间隔物，并且去除第一间隙和第三间隙中的间隔物。

公开(公告)号：US20160365344A1

公开(公告)日：2016-12-15

申请号：US14792591

申请日：2015-07-06

Applicant: United Microelectronics Corp.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Hon-Huei Liu ,  Chao-Hung Lin ,  Nan-Yuan Huang ,  Jyh-Shyang Jenq

IPC: H01L27/088 ,  H01L21/306 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L21/823431 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/42372 ,  H01L29/7842 ,  H01L29/785

Abstract: The present invention provides a semiconductor structure, including a substrate having a first fin structure and a second fin structure disposed thereon, a first isolation region located between the first fin structure and the second fin structure, a second isolation region located opposite the first fin structure from the first isolation region, and at least an epitaxial layer disposed on the side of the first fin structure and the second fin structure. The epitaxial layer has a bottom surface, the bottom surface extending from the first fin structure to the second fin structure, and the bottom surface is lower than a bottom surface of the first isolation region and a top surface of the second isolation region.

Abstract translation: 本发明提供了一种半导体结构，其包括具有第一鳍结构和设置在其上的第二鳍结构的衬底，位于第一鳍结构和第二鳍结构之间的第一隔离区，与第一鳍结构相对的第二隔离区 并且至少设置在第一鳍片结构和第二鳍片结构侧的外延层。 外延层具有从第一鳍结构延伸到第二鳍结构的底表面，底表面低于第一隔离区的底表面和第二隔离区的顶表面。

公开(公告)号：US09502410B1

公开(公告)日：2016-11-22

申请号：US14792591

申请日：2015-07-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Hon-Huei Liu ,  Chao-Hung Lin ,  Nan-Yuan Huang ,  Jyh-Shyang Jenq

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/28 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/306 ,  H01L27/092

CPC classification number: H01L21/823431 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/42372 ,  H01L29/7842 ,  H01L29/785

Abstract: The present invention provides a semiconductor structure, including a substrate having a first fin structure and a second fin structure disposed thereon, a first isolation region located between the first fin structure and the second fin structure, a second isolation region located opposite the first fin structure from the first isolation region, and at least an epitaxial layer disposed on the side of the first fin structure and the second fin structure. The epitaxial layer has a bottom surface, the bottom surface extending from the first fin structure to the second fin structure, and the bottom surface is lower than a bottom surface of the first isolation region and a top surface of the second isolation region.

Abstract translation: 本发明提供了一种半导体结构，其包括具有第一鳍结构和设置在其上的第二鳍结构的衬底，位于第一鳍结构和第二鳍结构之间的第一隔离区，与第一鳍结构相对的第二隔离区 并且至少设置在第一鳍片结构和第二鳍片结构侧的外延层。 外延层具有从第一鳍结构延伸到第二鳍结构的底表面，底表面低于第一隔离区的底表面和第二隔离区的顶表面。