公开(公告)号：US20170345819A1

公开(公告)日：2017-11-30

申请号：US15681570

申请日：2017-08-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hsin Liu ,  Pi-Hsuan Lai

IPC: H01L27/088 ,  H01L21/033 ,  H01L27/02 ,  H01L21/8234 ,  H01L27/11

CPC classification number: H01L27/088 ,  H01L21/0332 ,  H01L21/823456 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1116

Abstract: A semiconductor device is provided, including: a substrate having a first area and a second area; several first gate structures formed at the first area, and at least one of the first gate structures including a first hardmask on a first gate, and the first gate structure having a first gate length; several second gate structures formed at the second area, and at least one of the second gate structures including a second hardmask on a second gate, and the second gate structure having a second gate length. The first gate length is smaller than the second gate length, and the first hardmask contains at least a portion of nitrogen (N2)-based silicon nitride (SiN) which is free of OH concentration.

公开(公告)号：US10224324B2

公开(公告)日：2019-03-05

申请号：US15681570

申请日：2017-08-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hsin Liu ,  Pi-Hsuan Lai

IPC: H01L27/02 ,  H01L27/11 ,  H01L21/033 ,  H01L27/088 ,  H01L21/8234

Abstract: A semiconductor device is provided, including: a substrate having a first area and a second area; several first gate structures formed at the first area, and at least one of the first gate structures including a first hardmask on a first gate, and the first gate structure having a first gate length; several second gate structures formed at the second area, and at least one of the second gate structures including a second hardmask on a second gate, and the second gate structure having a second gate length. The first gate length is smaller than the second gate length, and the first hardmask contains at least a portion of nitrogen (N2)-based silicon nitride (SiN) which is free of OH concentration.

公开(公告)号：US20170309621A1

公开(公告)日：2017-10-26

申请号：US15136030

申请日：2016-04-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hsin Liu ,  Pi-Hsuan Lai

IPC: H01L27/088 ,  H01L21/033 ,  H01L27/02 ,  H01L21/8234 ,  H01L27/11

CPC classification number: H01L27/088 ,  H01L21/0332 ,  H01L21/823456 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1116

Abstract: A semiconductor device is provided, including: a substrate having a first area and a second area; several first gate structures formed at the first area, and at least one of the first gate structures including a first hardmask on a first gate, and the first gate structure having a first gate length; several second gate structures formed at the second area, and at least one of the second gate structures including a second hardmask on a second gate, and the second gate structure having a second gate length. The first gate length is smaller than the second gate length, and the first hardmask contains at least a portion of nitrogen (N2)-based silicon nitride (SiN) which is free of OH concentration.

公开(公告)号：US09793267B1

公开(公告)日：2017-10-17

申请号：US15136030

申请日：2016-04-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hsin Liu ,  Pi-Hsuan Lai

IPC: H01L27/088 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/033 ,  H01L27/11

CPC classification number: H01L27/088 ,  H01L21/0332 ,  H01L21/823456 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1116

Abstract: A semiconductor device is provided, including: a substrate having a first area and a second area; several first gate structures formed at the first area, and at least one of the first gate structures including a first hardmask on a first gate, and the first gate structure having a first gate length; several second gate structures formed at the second area, and at least one of the second gate structures including a second hardmask on a second gate, and the second gate structure having a second gate length. The first gate length is smaller than the second gate length, and the first hardmask contains at least a portion of nitrogen (N2)-based silicon nitride (SiN) which is free of OH concentration.

公开(公告)号：US09530696B1

公开(公告)日：2016-12-27

申请号：US14921514

申请日：2015-10-23

Applicant: United Microelectronics Corp.

Inventor： Wei-Hsin Liu ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Wei-Lun Hsu ,  Shang-Yi Yang ,  Pi-Hsuan Lai

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/321 ,  H01L21/311 ,  H01L21/3105

CPC classification number: H01L21/823431 ,  H01L21/823425 ,  H01L21/823437 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device is provided. A plurality of sacrificial gates and a plurality of sacrificial gate dielectric layers thereunder are formed on a substrate. An interlayer dielectric layer is filled between the sacrificial gates. A protective layer is formed on the interlayer dielectric layer. The sacrificial gates and the sacrificial gate dielectric layers are removed to form an opening, wherein the interlayer dielectric layer is protected by the protective layer from recessing. A stacked gate structure is formed in the opening, wherein the protective layer is removed.

Abstract translation: 提供一种制造半导体器件的方法。 在基板上形成有多个牺牲栅极和其下的多个牺牲栅介质层。 在牺牲栅极之间填充层间电介质层。 在层间电介质层上形成保护层。 去除牺牲栅极和牺牲栅极电介质层以形成开口，其中层间介电层被保护层保护而不被凹陷。 在开口中形成堆叠的栅极结构，其中保护层被去除。