公开(公告)号：US10475662B2

公开(公告)日：2019-11-12

申请号：US16158316

申请日：2018-10-12

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Feng-Yi Chang ,  Wei-Hsin Liu ,  Ying-Chih Lin ,  Jui-Min Lee ,  Gang-Yi Lin ,  Fu-Che Lee

IPC: H01L21/311 ,  H01L21/308 ,  H01L27/105 ,  H01L21/033

Abstract: A method of forming a semiconductor memory device includes following steps. First of all, a target layer is provided, and a mask structure is formed on the target layer, with the mask structure including a first mask layer a sacrificial layer and a second mask layer. The first mask layer and the second mask layer include the same material but in different containing ratio. Next, the second mask layer and the sacrificial layer are patterned, to form a plurality of mandrels. Then, a plurality of spacer patterns are formed to surround the mandrels, and then transferred into the first mask layer to form a plurality of opening not penetrating the first mask layer. Finally, the first mask layer is used as a mask to etch the target layer, to form a plurality of target patterns.

公开(公告)号：US10249706B1

公开(公告)日：2019-04-02

申请号：US15951185

申请日：2018-04-12

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Chia-Lung Chang ,  Wei-Hsin Liu ,  Po-Chun Chen ,  Yi-Wei Chen ,  Han-Yung Tsai ,  Tzu-Chin Wu ,  Shih-Fang Tzou

IPC: H01L49/02 ,  H01L27/108

Abstract: The present invention provides a semiconductor structure comprising a substrate, a cell region defined on the substrate, a plurality of lower electrodes of the capacitor structures located in the cell region, an top support structure, contacting a top region of the lower electrode structure, and at least one middle support structure located between the substrate and the top support structure, contacting a middle region of the lower electrode structure, wherein when viewed in a top view, the top support structure and the middle support structure do not completely overlapped with each other.

公开(公告)号：US20180190658A1

公开(公告)日：2018-07-05

申请号：US15859766

申请日：2018-01-02

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Mei-Ling Chen ,  Wei-Hsin Liu ,  Yi-Wei Chen ,  Chia-Lung Chang ,  Jui-Min Lee ,  Ching-Hsiang Chang ,  Tzu-Chin Wu ,  Shih-Fang Tzou

IPC: H01L27/108 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76834 ,  H01L21/02112 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02348 ,  H01L21/76825 ,  H01L21/823475 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/87 ,  H01L28/91

Abstract: The present invention provides a method for fabricating a semiconductor device, comprising at least the steps of: providing a substrate in which a memory region and a peripheral region are defined, the memory region includes a plurality of memory cells, each memory cell includes at least a first transistor and a capacitor, the peripheral region compress a second transistor, a first insulating layer is formed within the memory region and the peripheral region by an atomic layer deposition process, covering the capacitor of the memory cells in the memory region and the second transistor in the peripheral region, and a second insulating layer is formed, overlying the first insulating layer and the peripheral region. Finally, a contact structure is formed within the second insulating layer, and electrically connecting the second transistor.

公开(公告)号：US20160365315A1

公开(公告)日：2016-12-15

申请号：US14738943

申请日：2015-06-15

Applicant: United Microelectronics Corp.

Inventor： Wei-Hsin Liu ,  Bin-Siang Tsai

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L21/7682 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/32 ,  H01L21/76825 ,  H01L21/76834 ,  H01L23/485 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295

Abstract: A semiconductor process includes the following steps. Metal patterns are formed on a first dielectric layer. A modifiable layer is formed to cover the metal patterns and the first dielectric layer. A modification process is performed to modify a part of the modifiable layer on top sides of the metal patterns, thereby top masks being formed. A removing process is performed to remove a part of the modifiable layer on sidewalls of the metal patterns but preserve the top masks. A dielectric layer having voids under the top masks and between the metal patterns is formed. Moreover, the present invention also provides a semiconductor structure formed by said semiconductor process.

Abstract translation: 半导体工艺包括以下步骤。 金属图案形成在第一电介质层上。 形成可修饰层以覆盖金属图案和第一介电层。 执行修改处理以修改金属图案的顶侧上的可修改层的一部分，从而形成顶部掩模。 执行去除过程以去除金属图案的侧壁上的可修饰层的一部分，但保留顶部掩模。 形成在顶部掩模之下和金属图案之间具有空隙的电介质层。 此外，本发明还提供了由所述半导体工艺形成的半导体结构。

公开(公告)号：US09219151B1

公开(公告)日：2015-12-22

申请号：US14477214

申请日：2014-09-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hsin Liu ,  Tzu-Chin Wu

IPC: H01L21/31 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/7843 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/3105 ,  H01L29/7833

Abstract: A method for manufacturing a silicon nitride layer and a method for manufacturing a semiconductor structure applying the same are provided. The method for manufacturing a silicon nitride layer includes forming the silicon nitride layer and stressing the silicon nitride layer by a high density plasma chemical vapor deposition (HDPCVD) treatment.

Abstract translation: 提供了一种制造氮化硅层的方法及其制造应用该氮化硅层的半导体结构的方法。 制造氮化硅层的方法包括形成氮化硅层并通过高密度等离子体化学气相沉积（HDPCVD）处理来压制氮化硅层。

公开(公告)号：US20150206803A1

公开(公告)日：2015-07-23

申请号：US14158857

申请日：2014-01-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Hsin Liu ,  Tzu-Chin Wu ,  Jei-Ming Chen ,  Yu-Ren Wang ,  Chun-Yuan Wu ,  Chin-Fu Lin

IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3105

CPC classification number: H01L21/823462 ,  H01L21/31116 ,  H01L21/76837 ,  H01L21/823475

Abstract: A method of forming an inter-level dielectric layer including the following step is provided. Two gate structures are formed on a substrate. A first oxide layer is formed to conformally cover the two gate structures and the substrate. The first oxide layer is etched ex-situ by a high density plasma (HDP) etching process. A second oxide layer is formed in-situ on the first oxide layer and fills a gap between the two gate structures by a high density plasma (HDP) depositing process.

Abstract translation: 提供一种形成包括以下步骤的层间电介质层的方法。 在基板上形成两个栅极结构。 形成第一氧化物层以保形地覆盖两个栅极结构和衬底。 通过高密度等离子体（HDP）蚀刻工艺非原位蚀刻第一氧化物层。 在第一氧化物层上原地形成第二氧化物层，并通过高密度等离子体（HDP）沉积工艺填充两个栅极结构之间的间隙。

公开(公告)号：US10903328B2

公开(公告)日：2021-01-26

申请号：US15943717

申请日：2018-04-03

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Po-Chun Chen ,  Chia-Lung Chang ,  Yi-Wei Chen ,  Wei-Hsin Liu ,  Han-Yung Tsai

IPC: H01L29/423 ,  H01L21/28 ,  H01L27/108 ,  H01L21/762

Abstract: A method for fabricating semiconductor device includes the steps of: forming a shallow trench isolation (STI) in the substrate; removing part of the STI to form a trench in a substrate; forming an amorphous silicon layer in the trench and on the STI; performing an oxidation process to transform the amorphous silicon layer into a silicon dioxide layer; and forming a barrier layer and a conductive layer in the trench.

公开(公告)号：US20190206982A1

公开(公告)日：2019-07-04

申请号：US16297733

申请日：2019-03-11

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Tzu-Chin Wu ,  Wei-Hsin Liu ,  Yi-Wei Chen ,  Chia-Lung Chang ,  Jui-Min Lee ,  Po-Chun Chen ,  Li-Wei Feng ,  Ying-Chiao Wang ,  Wen-Chieh Lu ,  Chien-Ting Ho ,  Tsung-Ying Tsai ,  Kai-Ping Chen

IPC: H01L49/02 ,  H01L27/108 ,  H01L29/94

Abstract: A semiconductor memory device includes a semiconductor substrate, a first support layer, a first electrode, a capacitor dielectric layer, and a second electrode. The first support layer is disposed on the semiconductor substrate. The first electrode is disposed on the semiconductor substrate and penetrates the first support layer. The capacitor dielectric layer is disposed on the first electrode. The second electrode is disposed on the semiconductor substrate, and at least a part of the capacitor dielectric layer is disposed between the first electrode and the second electrode. The first support layer includes a carbon doped nitride layer, and a carbon concentration of a bottom portion of the first support layer is higher than a carbon concentration of a top portion of the first support layer.

公开(公告)号：US20180350673A1

公开(公告)日：2018-12-06

申请号：US15927106

申请日：2018-03-21

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Pin-Hong Chen ,  Chih-Chieh Tsai ,  Tzu-Chieh Chen ,  Kai-Jiun Chang ,  Chia-Chen Wu ,  Yi-An Huang ,  Tsun-Min Cheng ,  Yi-Wei Chen ,  Wei-Hsin Liu

IPC: H01L21/768 ,  H01L21/324 ,  H01L23/532

Abstract: A method of forming a semiconductor structure includes providing a material layer having a recess formed therein. A first tungsten metal layer is formed at a first temperature and fills the recess. An anneal process at a second temperature is then performed, wherein the second temperature is higher than the first temperature.

公开(公告)号：US20180190488A1

公开(公告)日：2018-07-05

申请号：US15859750

申请日：2018-01-02

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Mei-Ling Chen ,  Wei-Hsin Liu ,  Yi-Wei Chen ,  Ching-Hsiang Chang ,  Jui-Min Lee ,  Chia-Lung Chang ,  Tzu-Chin Wu ,  Shih-Fang Tzou

IPC: H01L21/02

CPC classification number: H01L21/02532 ,  H01L21/02422 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/02664

Abstract: The present invention provides a method for forming an amorphous silicon multiple layer structure, the method comprises the flowing steps: first, a substrate material layer is provided, next, a first amorphous silicon layer is formed on the substrate material layer, wherein the first amorphous silicon layer includes a plurality of hydrogen atoms disposed therein, afterwards, an UV curing process is performed to the first amorphous silicon layer, so as to remove the hydrogen atoms from the first amorphous silicon layer, finally, a second amorphous silicon layer is formed on the first amorphous silicon layer.