公开(公告)号：US11417654B2

公开(公告)日：2022-08-16

申请号：US16995941

申请日：2020-08-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Lun Hsu ,  Yung-Chien Kung ,  Ming-Tsung Yeh ,  Yan-Hsiu Liu ,  Am-Tay Luy ,  Yao-Pi Hsu ,  Ji-Fu Kung

IPC: H01L27/146 ,  H01L27/14 ,  H01L27/092 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/761 ,  H01L21/8234 ,  H01L29/78

Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.

公开(公告)号：US20210118889A1

公开(公告)日：2021-04-22

申请号：US17134193

申请日：2020-12-25

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Wei-Lun Hsu ,  Hung-Lin Shih ,  Che-Hung Huang ,  Ping-Cheng Hsu ,  Hsu-Yang Wang

IPC: H01L27/108 ,  H01L21/768 ,  H01L21/762

Abstract: A method for fabricating semiconductor device includes the steps of: forming a semiconductor layer on a substrate; removing part of the semiconductor layer and part of the substrate to form a trench; forming a liner in the trench; removing part of the liner to form a spacer adjacent to two sides of the trench; forming a conductive layer in the trench; forming a metal layer on the conductive layer; forming a mask layer on the metal layer; and patterning the mask layer, the metal layer, and the conductive layer to form a bit line structure.

公开(公告)号：US10475925B2

公开(公告)日：2019-11-12

申请号：US15985683

申请日：2018-05-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Lun Hsu ,  Hsin-Che Huang ,  Shyan-Liang Chou ,  Hung-Lin Shih

IPC: H01L21/762 ,  H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238

Abstract: A method for forming a complementary metal oxide semiconductor device is disclosed. First, a substrate having a first device region and a second device region is provided. A first trench is formed in the first device region and filled with a first material. A second trench is formed in the second device region and filled with a second material. The first material and the second material comprise different stresses. After that, a first gate structure and a second gate structure are formed on the first material and the second material and completely covering the first trench and the second trench, respectively.

公开(公告)号：US20190279989A1

公开(公告)日：2019-09-12

申请号：US15943721

申请日：2018-04-03

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Wei-Lun Hsu ,  Hung-Lin Shih ,  Che-Hung Huang ,  Ping-Cheng Hsu ,  Hsu-Yang Wang

IPC: H01L27/108 ,  H01L21/762 ,  H01L21/768

Abstract: According to an embodiment of the present invention, a method for fabricating semiconductor device includes the steps of: forming a semiconductor layer on a substrate; removing part of the semiconductor layer and part of the substrate to form a trench; forming a liner in the trench; removing part of the liner to form a spacer adjacent to two sides of the trench; and forming a bit line structure in the trench.

公开(公告)号：US20150079754A1

公开(公告)日：2015-03-19

申请号：US14548248

申请日：2014-11-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Chung Wang ,  Wei-Lun Hsu ,  Shan-Shi Huang ,  Ke-Feng Lin ,  Te-Yuan Wu

IPC: H01L29/66 ,  H01L21/033 ,  H01L29/08 ,  H01L21/266 ,  H01L29/40 ,  H01L29/06

CPC classification number: H01L29/66681 ,  H01L21/0334 ,  H01L21/266 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/7816

Abstract: The present invention provides a method of fabricating a HV MOS transistor device, including forming a deep well in a substrate, and the deep well; forming a first doped region in the deep well, and the first doped region, wherein a doping concentration of the first doped region and a doping concentration of the deep well in at least one electric field concentration region has a first ratio, the doping concentration of the first doped region and the doping concentration of the deep well outside the electric field concentration region has a second ratio, and the first ratio is greater than the second ratio; and forming a high voltage well in the substrate, and forming a second doped region and a third doped region respectively in the deep well and in the high voltage well.

Abstract translation: 本发明提供一种制造HV MOS晶体管器件的方法，包括在衬底和深阱中形成深阱; 在所述深阱中形成第一掺杂区域和所述第一掺杂区域，其中所述第一掺杂区域的掺杂浓度和所述深阱在至少一个电场浓度区域中的掺杂浓度具有第一比率，所述第一掺杂区域的掺杂浓度 第一掺杂区域和电场浓度区外的深阱的掺杂浓度具有第二比例，第一比值大于第二比例; 以及在所述衬底中形成高电压阱，以及分别在所述深阱和所述高电压阱中形成第二掺杂区和第三掺杂区。

公开(公告)号：US11665888B2

公开(公告)日：2023-05-30

申请号：US17134193

申请日：2020-12-25

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Wei-Lun Hsu ,  Hung-Lin Shih ,  Che-Hung Huang ,  Ping-Cheng Hsu ,  Hsu-Yang Wang

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H10B12/485 ,  H01L21/76224 ,  H01L21/76877 ,  H10B12/053 ,  H01L21/823481 ,  H01L21/823878 ,  H10B12/482

Abstract: A method for fabricating semiconductor device includes the steps of: forming a semiconductor layer on a substrate; removing part of the semiconductor layer and part of the substrate to form a trench; forming a liner in the trench; removing part of the liner to form a spacer adjacent to two sides of the trench; forming a conductive layer in the trench; forming a metal layer on the conductive layer; forming a mask layer on the metal layer; and patterning the mask layer, the metal layer, and the conductive layer to form a bit line structure.

公开(公告)号：US20220271035A1

公开(公告)日：2022-08-25

申请号：US17741123

申请日：2022-05-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Lun Hsu ,  Yung-Chien Kung ,  Ming-Tsung Yeh ,  Yan-Hsiu Liu ,  Am-Tay Luy ,  Yao-Pi Hsu ,  Ji-Fu Kung

IPC: H01L27/092 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/761

Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.

公开(公告)号：US20200098755A1

公开(公告)日：2020-03-26

申请号：US16697800

申请日：2019-11-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Lun Hsu ,  Yung-Chien Kung ,  Ming-Tsung Yeh ,  Yan-Hsiu Liu ,  Am-Tay Luy ,  Yao-Pi Hsu ,  Ji-Fu Kung

IPC: H01L27/092 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/761

Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.

公开(公告)号：US10008599B1

公开(公告)日：2018-06-26

申请号：US15446009

申请日：2017-03-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Lun Hsu ,  Hsin-Che Huang ,  Shyan-Liang Chou ,  Hung-Lin Shih

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L29/7846 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0649

Abstract: A complementary metal oxide semiconductor (CMOS) device is disclosed. The CMOS device includes a substrate with a first device region and a second device region formed thereon. A first isolation structure is formed in the first device region, and includes a first trench filled with a first material. A second isolation structure is formed in the second device region and includes a second trench filled with a second material. The first material and the second material have different stresses. A first gate structure is disposed atop the first material and completely covering the first trench. A second gate structure is disposed atop the second material and completely covering the second trench.

公开(公告)号：US20150137176A1

公开(公告)日：2015-05-21

申请号：US14083551

申请日：2013-11-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Lun Hsu ,  Chung-Yi Chiu

IPC: H01L29/739

CPC classification number: H01L29/7395 ,  H01L29/0834

Abstract: A semiconductor power device is provided, comprising a substrate of a first conductive type, a buffering layer of a second conductive type formed on the substrate, a voltage supporting layer formed on the buffering layer, and alternating sections of different conductive types formed at the substrate. The voltage supporting layer comprises first semiconductor regions of the first conductive type and second semiconductor regions of the second conductive type, wherein the first semiconductor regions and the second semiconductor regions are alternately arranged. The alternating section and the buffering layer form a segmented structure of alternated conductive types, which is used as an anode of the semiconductor device.

Abstract translation: 提供了一种半导体功率器件，包括第一导电类型的衬底，形成在衬底上的第二导电类型的缓冲层，形成在缓冲层上的电压支撑层，以及形成在衬底上的不同导电类型的交替部分 。 电压支撑层包括第一导电类型的第一半导体区域和第二导电类型的第二半导体区域，其中第一半导体区域和第二半导体区域交替布置。 交替部分和缓冲层形成交替导电类型的分段结构，其用作半导体器件的阳极。