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公开(公告)号：US09047658B2
公开(公告)日：2015-06-02
申请号：US14071667
申请日：2013-11-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Te-Hsien Hsieh , Ming-Jui Chen , Cheng-Te Wang , Ping-I Hsieh , Jing-Yi Lee
CPC classification number: G06T7/0004 , G03F1/36 , G06K9/00 , G06T7/001 , G06T2207/30148
Abstract: A calculation method of optical proximity correction includes providing at least a feature pattern to a computer system. At least a first template and a second template are defined so that portions of the feature pattern are located in the first template and the rest of the feature pattern is located in the second template. The first template and the second template have a common boundary. Afterwards, a first calculation zone is defined to overlap an entire first template and portions of the feature pattern out of the first template. Edges of the feature pattern within the first calculation zone are then fragmented from the common boundary towards two ends of the feature pattern so as to generate at least two first beginning segments respectively at two sides of the common boundary. Finally, positions of the first beginning segments are adjusted so as to generate first adjusted segments.
Abstract translation: 光学邻近校正的计算方法包括至少向计算机系统提供特征图案。 定义至少第一模板和第二模板，使得特征图案的部分位于第一模板中，并且特征图案的其余部分位于第二模板中。 第一个模板和第二个模板有一个共同的边界。 之后，定义第一计算区域以将整个第一模板和第一模板中的特征模式的部分重叠。 然后将第一计算区域内的特征图案的边缘从公共边界分割成特征图案的两端，以便分别在公共边界的两侧产生至少两个第一开始段。 最后，调整第一起始段的位置，以产生第一调整段。
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Patent Agency Ranking
公开(公告)号：US20170024506A1
公开(公告)日：2017-01-26
申请号：US14807869
申请日：2015-07-23
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Shih-Ming Kuo , Ming-Jui Chen , Te-Hsien Hsieh , Ping-I Hsieh , Jing-Yi Lee , Yan-Chun Chen
CPC classification number: G06F17/5072 , G03F1/36 , G06F17/5081
Abstract: A method for optimizing an integrated circuit layout design includes the following steps. A first integrated circuit layout design including a metal line feature having several metal lines and a second integrated circuit layout design including a hole feature having several holes are obtained. A line-end hole feature of the hole feature is selected by piecing the metal line feature with the hole feature. The line-end hole feature is classified into a single hole feature and a redundant hole feature by spacings between the adjacent holes by a computer system.
Abstract translation: 一种用于优化集成电路布局设计的方法包括以下步骤。 获得包括具有多个金属线的金属线特征和包括具有多个孔的孔特征的第二集成电路布局设计的第一集成电路布局设计。 通过将具有孔特征的金属线特征拼接，选择孔特征的线端孔特征。 线端孔特征通过计算机系统由相邻孔之间的间隔分为单孔特征和冗余孔特征。
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公开(公告)号：US20140256132A1
公开(公告)日：2014-09-11
申请号：US13787912
申请日：2013-03-07
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chia-Wei Huang , Ming-Jui Chen , Ting-Cheng Tseng , Ping-I Hsieh
IPC: H01L21/308
CPC classification number: H01L21/308 , H01L27/1116
Abstract: A method for patterning a semiconductor structure is provided. The method comprises following steps. A first mask defining a first pattern in a first region and a second pattern in a second region adjacent to the first region is provided. The first pattern defined by the first mask is transferred to a first film structure in the first region, and the second pattern defined by the first mask is transferred to the first film structure in the second region. A second film structure is formed on the first film structure. A second mask defining a third pattern in the first region is provided. At least 50% of a part of the first region occupied by the first pattern defined by the first mask is identical with a part of the first region occupied by the third pattern defined by the second mask.
Abstract translation: 提供了一种图案化半导体结构的方法。 该方法包括以下步骤。 提供了在第一区域中限定第一图案的第一掩模和与第一区域相邻的第二区域中的第二图案。 由第一掩模限定的第一图案被转移到第一区域中的第一膜结构，并且由第一掩模限定的第二图案被转移到第二区域中的第一膜结构。 在第一膜结构上形成第二膜结构。 提供了在第一区域中限定第三图案的第二掩模。 由第一掩模限定的第一图案占据的第一区域的一部分的至少50％与由第二掩模限定的第三图案占据的第一区域的一部分相同。
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公开(公告)号：US08822328B1
公开(公告)日：2014-09-02
申请号：US13787912
申请日：2013-03-07
Applicant: United Microelectronics Corp.
Inventor： Chia-Wei Huang , Ming-Jui Chen , Ting-Cheng Tseng , Ping-I Hsieh
IPC: H01L21/4763 , H01L21/302 , H01L21/308
CPC classification number: H01L21/308 , H01L27/1116
Abstract: A method for patterning a semiconductor structure is provided. The method comprises following steps. A first mask defining a first pattern in a first region and a second pattern in a second region adjacent to the first region is provided. The first pattern defined by the first mask is transferred to a first film structure in the first region, and the second pattern defined by the first mask is transferred to the first film structure in the second region. A second film structure is formed on the first film structure. A second mask defining a third pattern in the first region is provided. At least 50% of a part of the first region occupied by the first pattern defined by the first mask is identical with a part of the first region occupied by the third pattern defined by the second mask.
Abstract translation: 提供了一种图案化半导体结构的方法。 该方法包括以下步骤。 提供了在第一区域中限定第一图案的第一掩模和与第一区域相邻的第二区域中的第二图案。 由第一掩模限定的第一图案被转移到第一区域中的第一膜结构，并且由第一掩模限定的第二图案被转移到第二区域中的第一膜结构。 在第一膜结构上形成第二膜结构。 提供了在第一区域中限定第三图案的第二掩模。 由第一掩模限定的第一图案占据的第一区域的一部分的至少50％与由第二掩模限定的第三图案占据的第一区域的一部分相同。
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公开(公告)号：US09747404B2
公开(公告)日：2017-08-29
申请号：US14807869
申请日：2015-07-23
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Shih-Ming Kuo , Ming-Jui Chen , Te-Hsien Hsieh , Ping-I Hsieh , Jing-Yi Lee , Yan-Chun Chen
CPC classification number: G06F17/5072 , G03F1/36 , G06F17/5081
Abstract: A method for optimizing an integrated circuit layout design includes the following steps. A first integrated circuit layout design including a metal line feature having several metal lines and a second integrated circuit layout design including a hole feature having several holes are obtained. A line-end hole feature of the hole feature is selected by piecing the metal line feature with the hole feature. The line-end hole feature is classified into a single hole feature and a redundant hole feature by spacings between the adjacent holes by a computer system.
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公开(公告)号：US20150125063A1
公开(公告)日：2015-05-07
申请号：US14071667
申请日：2013-11-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Te-Hsien Hsieh , Ming-Jui Chen , Cheng-Te Wang , Ping-I Hsieh , Jing-Yi Lee
IPC: G06T7/00
CPC classification number: G06T7/0004 , G03F1/36 , G06K9/00 , G06T7/001 , G06T2207/30148
Abstract: A calculation method of optical proximity correction includes providing at least a feature pattern to a computer system. At least a first template and a second template are defined so that portions of the feature pattern are located in the first template and the rest of the feature pattern is located in the second template. The first template and the second template have a common boundary. Afterwards, a first calculation zone is defined to overlap an entire first template and portions of the feature pattern out of the first template. Edges of the feature pattern within the first calculation zone are then fragmented from the common boundary towards two ends of the feature pattern so as to generate at least two first beginning segments respectively at two sides of the common boundary. Finally, positions of the first beginning segments are adjusted so as to generate first adjusted segments.
Abstract translation: 光学邻近校正的计算方法包括至少向计算机系统提供特征图案。 定义至少第一模板和第二模板，使得特征图案的部分位于第一模板中，并且特征图案的其余部分位于第二模板中。 第一个模板和第二个模板有一个共同的边界。 之后，定义第一计算区域以将整个第一模板和第一模板中的特征模式的部分重叠。 然后将第一计算区域内的特征图案的边缘从公共边界分割成特征图案的两端，以便分别在公共边界的两侧产生至少两个第一开始段。 最后，调整第一起始段的位置，以产生第一调整段。
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