公开(公告)号：US11381247B1

公开(公告)日：2022-07-05

申请号：US17225074

申请日：2021-04-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Hong Hsu ,  Po-Hua Chen ,  Yu-Yee Liow ,  Chih-Wei Wu ,  Hsuan-Chih Yeh

IPC: H03D3/24 ,  H03L7/089 ,  H03L7/10 ,  H03L7/083 ,  H03L7/095

Abstract: An apparatus includes a phase-locked loop and a jitter detection circuit. A method of detecting a jitter in the apparatus includes the phase-locked loop generating a lead control signal and a lag control signal according to a reference clock and a feedback clock, the jitter detection circuit generating a jitter signal according to the lead control signal and the lag control signal, the jitter detection circuit generating a jitter window signal according to the jitter signal, the jitter detection circuit identifying jitters in the clock signal according to the jitter signal and the jitter window signal, and the jitter detection circuit outputting a jitter indication signal according to the number of jitters identified.

公开(公告)号：US12250002B2

公开(公告)日：2025-03-11

申请号：US18127262

申请日：2023-03-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Hua Chen ,  Yu-Yee Liow ,  Chih-Wei Wu ,  Wen-Hong Hsu ,  Hsuan-Chih Yeh ,  Pei-Wen Sun

IPC: H03M1/46

Abstract: A SAR ADC includes: a sample-hold (S/H) circuit sampling an input voltage to generate a S/H output signal; a DAC generating a DAC output signal; a comparator comparing the DAC output signal with the S/H output signal to generate a comparison output signal; a SAR combinational digital circuit group; a multiplexer circuit; and a plurality of registers for registering the comparison output signal as register output signals and outputting as an output signal of the SAR ADC. The SAR combinational digital circuit group generates a plurality of first and second SAR output signals based on the register output signals. The multiplexer circuit is controlled by on the register output signals to select among the first and the second SAR output signals as a plurality of multiplexer output signals for sending to the DAC. A capacitor coupling relationship of the DAC is controlled by the multiplexer output signals.

公开(公告)号：US09143143B2

公开(公告)日：2015-09-22

申请号：US14153919

申请日：2014-01-13

Applicant: United Microelectronics Corp.

Inventor： Po-Hua Chen ,  Yu-Yee Liow ,  Wen-Hong Hsu ,  Hsueh-Chen Cheng

IPC: H03L7/00 ,  H03L7/183 ,  H03L7/095 ,  H03L7/093

CPC classification number: H03L7/183 ,  H03L3/00 ,  H03L7/093 ,  H03L7/095 ,  H03L2207/08

Abstract: A circuit and a method for restarting up a VCO of a PLL are introduced herein. The VCO restart up circuit receives a power down signal, an external signal, a clock output from the VCO and generates a trigger signal to the VCO to trigger the VCO clock to leave a stable mode. In other words, if the VCO clock is in the stable mode, the VCO restart up circuit generates one or more than one pulse on a trigger signal to restart up the VCO. Oppositely, if the VCO is not in the stable mode, there is no pulse on the trigger signal generated by the VCO restart up circuit and the VCO needs not to be restarted up.

Abstract translation: 本文介绍了一种用于重新启动PLL的VCO的电路和方法。 VCO重新启动电路接收掉电信号，外部信号，从VCO输出的时钟，并产生到VCO的触发信号，以触发VCO时钟离开稳定模式。 换句话说，如果VCO时钟处于稳定模式，则VCO重新启动电路在触发信号上产生一个或多于一个脉冲以重新启动VCO。 相反地​​，如果VCO不是稳定模式，则由VCO重启电路产生的触发信号上没有脉冲，VCO不需要重启。

公开(公告)号：US20250080129A1

公开(公告)日：2025-03-06

申请号：US18464291

申请日：2023-09-11

Applicant: United Microelectronics Corp.

Inventor： Hsuan Chih Yeh ,  Yu-Yee Liow ,  Wen-Hong Hsu ,  Po-Hua Chen ,  Chihwei Wu ,  Pei Wen Sun

IPC: H03M1/10

Abstract: According to an aspect of the disclosure, the disclosure provides an ADC which includes not limited to: a DAC configured to generate a positive input delta voltage and a negative input delta voltage, a comparator electrically connected to the DAC and configured to receive the positive input delta voltage to generate a first digital output value and to receive the negative input delta voltage to generate a second digital output value, a logic circuit configured to receive, from the comparator, the first digital output value and the second digital output value to generate a digital quantization code according to half of a sum of the first digital output value and the second digital output value, and a calibration circuit configured to receive the digital quantization code from the logic circuit and calibrate an output of the ADC according to the digital quantization code to eliminate an offset error value.

公开(公告)号：US09160352B1

公开(公告)日：2015-10-13

申请号：US14287772

申请日：2014-05-27

Applicant: United Microelectronics Corp.

Inventor： Po-Hua Chen ,  Yu-Yee Liow ,  Wen-Hong Hsu ,  Hsueh-Chen Cheng ,  Ya-Nan Mou ,  Yuan-Hui Chen

IPC: H03L7/06 ,  H03L7/099 ,  H03L7/08 ,  H03L7/085

CPC classification number: H03L3/00 ,  H03L7/089 ,  H03L7/099

Abstract: A phase-locked loop (PLL) and a method for controlling the PLL are provided. The PLL includes a phase detector, a charge pump, a voltage-controlled oscillator (VCO), a feedback frequency divider, and a detector circuit. The phase detector generates a direction signal according to a comparison between phases of a first clock signal and a second clock signal. The charge pump converts the direction signal into a control voltage. The VCO generates a third clock signal. The control voltage controls a frequency of the third clock signal. The feedback frequency divider divides the frequency of the third clock signal to generate the second clock signal. The detector circuit sends a pulse signal to restart the VCO when the control voltage conforms to a preset condition.

Abstract translation: 提供锁相环（PLL）和控制PLL的方法。 PLL包括相位检测器，电荷泵，压控振荡器（VCO），反馈分频器和检测器电路。 相位检测器根据第一时钟信号和第二时钟信号的相位之间的比较来产生方向信号。 电荷泵将方向信号转换成控制电压。 VCO产生第三个时钟信号。 控制电压控制第三时钟信号的频率。 反馈分频器分频第三时钟信号的频率以产生第二时钟信号。 当控制电压符合预设条件时，检测器电路发送脉冲信号重新启动VCO。

公开(公告)号：US08587462B1

公开(公告)日：2013-11-19

申请号：US13663485

申请日：2012-10-30

Applicant: United Microelectronics Corp.

Inventor： Hsueh-Chen Cheng ,  Wen-Hong Hsu ,  Po-Hua Chen ,  Yu-Yee Liow

IPC: H03M1/66

CPC classification number: H03M1/067 ,  H03M1/685 ,  H03M1/747

Abstract: A digital-to-analog converter includes a clock driver, a first decoder, a second decoder, a current source matrix, a pseudo random mode generator and at least one multiplexer. The first decoder and the second decoder are coupled to the clock driver. The current source matrix is coupled to the first decoder, and the pseudo random mode generator is used to randomly output a set of selecting signals. Each multiplexer of the at least one multiplexer includes a plurality of input ends coupled to a plurality of output ends of the second decoder, an output end coupled to the current source matrix, and a select end coupled to the pseudo random mode generator for controlling the output end to output a bit signal inputted from the input ends of the multiplexer according to one selecting signal of the set of selecting signals.

Abstract translation: 数模转换器包括时钟驱动器，第一解码器，第二解码器，电流源矩阵，伪随机模式发生器和至少一个复用器。 第一解码器和第二解码器耦合到时钟驱动器。 电流源矩阵耦合到第一解码器，并且伪随机模式发生器用于随机输出一组选择信号。 所述至少一个多路复用器的每个多路复用器包括耦合到第二解码器的多个输出端的多个输入端，耦合到电流源矩阵的输出端，以及耦合到伪随机模式发生器的选择端，用于控制 输出端，根据该组选择信号的一个选择信号，输出从复用器的输入端输入的位信号。

公开(公告)号：US20150200626A1

公开(公告)日：2015-07-16

申请号：US14153919

申请日：2014-01-13

Applicant: United Microelectronics Corp.

Inventor： Po-Hua Chen ,  Yu-Yee Liow ,  Wen-Hong Hsu ,  Hsueh-Chen Cheng

IPC: H03B5/06

CPC classification number: H03L7/183 ,  H03L3/00 ,  H03L7/093 ,  H03L7/095 ,  H03L2207/08

Abstract: A circuit and a method for restarting up a VCO of a PLL are introduced herein. The VCO restart up circuit receives a power down signal, an external signal, a clock output from the VCO and generates a trigger signal to the VCO to trigger the VCO clock to leave a stable mode. In other words, if the VCO clock is in the stable mode, the VCO restart up circuit generates one or more than one pulse on a trigger signal to restart up the VCO. Oppositely, if the VCO is not in the stable mode, there is no pulse on the trigger signal generated by the VCO restart up circuit and the VCO needs not to be restarted up.

Abstract translation: 本文介绍了一种用于重新启动PLL的VCO的电路和方法。 VCO重新启动电路接收掉电信号，外部信号，从VCO输出的时钟，并产生到VCO的触发信号，以触发VCO时钟离开稳定模式。 换句话说，如果VCO时钟处于稳定模式，则VCO重新启动电路在触发信号上产生一个或多于一个脉冲以重新启动VCO。 相反地​​，如果VCO不是稳定模式，则由VCO重启电路产生的触发信号上没有脉冲，VCO不需要重启。

公开(公告)号：US08669897B1

公开(公告)日：2014-03-11

申请号：US13668339

申请日：2012-11-05

Applicant: United Microelectronics Corp.

Inventor： Po-Hua Chen ,  Hsueh-Chen Cheng ,  Wen-Hong Hsu ,  Yu-Yee Liow

IPC: H03M1/38

CPC classification number: H03M1/125 ,  H03M1/462

Abstract: An asynchronous successive approximation register analog-to-digital converter includes a clock generator, a logic control unit, a sample and hold circuit, a digital-to-analog converter and a comparator. The clock generator is used to generate a clock signal. The logic control unit is for generating a sample and hold clock according to the clock signal. The sample and hold circuit is for sampling an analog signal according to the sample and hold clock to obtain and hold a sampling signal. The digital-to-analog converter is for generating a reference value according to a digital value transmitted from the logic control unit. The comparator is for generating a comparison value according to the sampling signal and the reference value.

Abstract translation: 异步逐次逼近寄存器模数转换器包括时钟发生器，逻辑控制单元，采样和保持电路，数模转换器和比较器。 时钟发生器用于产生时钟信号。 逻辑控制单元用于根据时钟信号产生采样和保持时钟。 采样和保持电路用于根据采样和保持时钟采样模拟信号，以获取并保持采样信号。 数模转换器用于根据从逻辑控制单元发送的数字值产生参考值。 比较器用于根据采样信号和参考值产生比较值。