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公开(公告)号：US6108771A
公开(公告)日：2000-08-22
申请号：US15870
申请日：1998-01-29
CPC分类号： G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A system and method for register renaming and allocation in an out-of-order processing system which allows the use of a minimum number of physical registers is described. A link list allows concatenation of a physical register representing a certain instance of the corresponding logical register to the physical register representing the next instance of the same logical register. By adding and removing links in this link list, it is possible to manage the assignment of physical registers to logical registers dynamically. Both the physical registers representing speculative instances and the physical registers representing in-order instances are administrated together. This is done by means of an in-order list, which indicates the physical registers that actually represent the architected state of the machine.
摘要翻译： 描述了允许使用最少数量的物理寄存器的无序处理系统中的寄存器重命名和分配的系统和方法。 链接列表允许将表示相应逻辑寄存器的某个实例的物理寄存器连接到表示相同逻辑寄存器的下一个实例的物理寄存器。 通过添加和删除此链接列表中的链接，可以动态地管理物理寄存器到逻辑寄存器的分配。 表示推测实例的物理寄存器和表示顺序实例的物理寄存器都被一起管理。 这是通过一个顺序列表来完成的，它列出了实际表示机器的架构状态的物理寄存器。
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公开(公告)号：US5761734A
公开(公告)日：1998-06-02
申请号：US689762
申请日：1996-08-13
CPC分类号： G06F9/52 , G06F12/1072
摘要： A process is disclosed to serialize instructions that are to be processed serially in a multiprocessor system, with the use of a token, where the token can be assigned on request to one of the processors, which thereupon has the right to execute the command. If the command consists of dristibuted tasks, the token remains blocked until the last dependent task belonging to the command has also been executed. It is only then that the token can be assigned to another instruction. Moreover, a device is described to manage this token, which features three states: a first state, in which the token is available, a second state, in which the token is assigned to one of the processors, and a third state, in which the token is blocked, because dependent tasks still have to be carried out. Moreover, a circuit is disclosed with which the token principle that is introduced can be implemented in a simple manner. The token is only available if none of the processors i is in possession of the token and if no dependent task is pending at any of the processors. The OR chaining of signals to form a signal C which is set if the token is not available represents the basic circuitry with which the serialisation of commands consisting of distributed tasks is carried out. The invention is applied particularly in the case of commands such as IPTE (invalidate page-table entry) and SSKE (set storage key extended), which modify the address translation tables in the memory that are used in common by all processors.
摘要翻译： 公开了一种过程，其使用令牌来序列化要在多处理器系统中串行处理的指令，其中令牌可以根据请求分配给一个处理器，其中有一个执行命令。 如果命令由dristibuted任务组成，令牌将保持阻塞，直到属于命令的最后一个任务也已被执行。 只有令牌可以分配给另一个指令。 此外，描述了一种用于管理该令牌的设备，其特征在于三个状态：其中令牌可用的第一状态，其中将令牌分配给处理器之一的第二状态和第三状态，其中 令牌被阻止，因为依赖的任务仍然需要执行。 此外，公开了可以以简单的方式实现引入的令牌原理的电路。 该令牌仅在没有任何一个处理器拥有该令牌并且任何一个处理器中未依赖任务的情况下可用。 如果令牌不可用，则形成信号C的OR链接形成表示执行由分散任务组成的命令的串行化的基本电路。 本发明特别适用于诸如IPTE（无效页表条目）和SSKE（设置存储密钥扩展）的命令的情况，其修改由所有处理器共同使用的存储器中的地址转换表。
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3.发明授权Data processing apparatus and method for correcting faulty microcode in a ROM device via a flag microinstruction in a RAM device including corrected microcode 失效一种数据处理装置和方法，用于通过包括经校正的微代码的RAM装置中的标志微指令来校正ROM装置中的有缺陷的微代码
公开(公告)号：US5870601A
公开(公告)日：1999-02-09
申请号：US750756
申请日：1996-12-16
CPC分类号： G06F9/268 , G06F8/66 , G06F9/30145 , G06F9/328
摘要： The present invention relates to a data processing apparatus which comprises a microprogrammable processor 1, a random access control store 4 and a read only control store 5 for storage of microinstructions. The random access control store includes a flag microinstruction (REPmark1) for indicating that another microinstruction (add W, 2, W1), stored in the read only control store 5, is faulty. The control stores are coupled to a multiplexer 8 and are adapted to output the microinstructions in parallel to the multiplexer 8 which is in turn coupled to the processor and which selectively provides output from either the random access control store or the read only control store to the processor 1. The apparatus also includes a decoder coupled to the random access control store for observing the microinstructions output therefrom. The decoder is further coupled to inhibiting logic in the processor and outputs a signal if the flag microinstruction is output from the random access control store. The signal causes the inhibiting logic in the processor to inhibit the processor from carrying out the faulty microinstruction.
摘要翻译： PCT No.PCT / EP95 / 03394 371日期1996年12月16日第 102（e）日期1996年12月16日PCT提交1995年8月29日PCT公布。 公开号WO97 / 08618 日期1997年3月6日本发明涉及一种数据处理装置，其包括微程序处理器1，随机存取控制存储器4和用于存储微指令的只读控制存储器5。 随机访问控制存储器包括用于指示存储在只读控制存储器5中的另一微指令（添加W，2，W1）有故障的标志微指令（REPmark1）。 控制存储器耦合到多路复用器8并且适于与多路复用器8并行地输出微指令，多路复用器8又耦合到处理器，并且选择性地将随机存取控制存储器或只读控制存储器的输出提供给 该装置还包括耦合到随机存取控制存储器的解码器，用于观察从其输出的微指令。 如果从随机存取控制存储器输出标志微指令，则解码器还耦合到禁止处理器中的逻辑并输出信号。 该信号使处理器中的禁止逻辑禁止处理器执行故障微指令。
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公开(公告)号：US6032233A
公开(公告)日：2000-02-29
申请号：US886304
申请日：1997-07-01
申请人： Peter Loffler , Erwin Pfeffer , Thomas Pfluger , Hans-Werner Tast
发明人： Peter Loffler , Erwin Pfeffer , Thomas Pfluger , Hans-Werner Tast
CPC分类号： G11C8/16
摘要： A set of storage devices together with a method for storing data to the storage devices and retrieving data from the storage devices is presented. The set of storage devices provide the function of a multi-writeport cell through the use of a set of single-writeport cells. The storage devices allow for multiple write accesses. Information contained in the set of storage device is represented by all of the devices together. The stored information may be retrieved via a read operation which accesses a subset of the set of storage devices. A write operation is a staged operation: First, the contents of all of the storage devices which are not to be modified are read. Next, the values that are to be written to a subset B of the set of storage devices are calculated in a way that the contents and the values of subset B together represent the desired result.
摘要翻译： 提供一组存储设备以及用于将数据存储到存储设备并从存储设备检索数据的方法。 该组存储设备通过使用一组单写入单元提供多写入单元的功能。 存储设备允许多次写访问。 包含在该组存储设备中的信息由所有设备一起表示。 存储的信息可以通过访问该组存储设备的子集的读取操作来检索。 写入操作是分阶段操作：首先，读取所有不被修改的存储设备的内容。 接下来，以将子集B的内容和值一起表示期望结果的方式计算要写入该组存储装置的子集B的值。
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公开(公告)号：US08751749B2
公开(公告)日：2014-06-10
申请号：US13159590
申请日：2011-06-14
摘要： Data caching for use in a computer system including a lower cache memory and a higher cache memory. The higher cache memory receives a fetch request. It is then determined by the higher cache memory the state of the entry to be replaced next. If the state of the entry to be replaced next indicates that the entry is exclusively owned or modified, the state of the entry to be replaced next is changed such that a following cache access is processed at a higher speed compared to an access processed if the state would stay unchanged.
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公开(公告)号：US20130339615A1
公开(公告)日：2013-12-19
申请号：US13524386
申请日：2012-06-15
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F9/467 , G06F11/1474 , G06F12/0828
摘要： Embodiments relate to controlling observability of transactional and non-transactional stores. An aspect includes receiving one or more store instructions. The one or more store instructions are initiated within an active transaction and include store data. The active transaction effectively delays committing stores to memory until successful completion of the active transaction. The store data is stored in a local storage buffer causing alterations to the local storage buffer from a first state to a second state. A signal is received that the active transaction has terminated. If the active transaction has terminated abnormally then: the local storage buffer is reverted back to the first state if the store data was stored by a transactional store instruction, and is propagated to a shared cache if the store instruction is non-transactional.
摘要翻译： 实施例涉及控制事务和非交易存储的可观察性。 一方面包括接收一个或多个存储指令。 一个或多个存储指令在活动事务中启动并且包括存储数据。 活动事务有效地延迟将存储提交到存储器，直到成功完成活动事务。 存储数据存储在本地存储缓冲器中，导致本地存储缓冲器从第一状态到第二状态的改变。 接收到有效事务终止的信号。 如果活动事务已经异常终止，则：如果存储数据由事务存储指令存储，则本地存储缓冲区被恢复到第一状态，并且如果存储指令是非事务性的则将其传播到共享高速缓存。
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7.发明申请METHOD TO VERIFY AN IMPLEMENTED COHERENCY ALGORITHM OF A MULTI PROCESSOR ENVIRONMENT 失效验证多处理器环境的实现的相似算法的方法公开(公告)号：US20100146210A1
公开(公告)日：2010-06-10
申请号：US12328242
申请日：2008-12-04
CPC分类号： G06F12/0815
摘要： A method to verify an implemented coherency algorithm of a multi processor environment on a single processor model is described, comprising the steps of: generating a reference model reflecting a private cache hierarchy of a single processor within a multi processor environment, stimulating the private cache hierarchy with simulated requests and/or cross invalidations from a core side and/or from a nest side, augmenting all data available in the private cache hierarchy with two construction dates and two expiration dates, set based on interface events, wherein multi processor coherency is not observed if the cache hierarchy ever returns data to the processor with an expiration date that is older than the latest construction date of all data used before. Further a single processor model and a computer program product to execute said method are described.
摘要翻译： 描述了在单个处理器模型上验证多处理器环境的实现的一致性算法的方法，包括以下步骤：生成反映多处理器环境内的单个处理器的专用高速缓存层级的参考模型，以刺激专用高速缓存层级 具有来自核心侧和/或来自嵌套侧的模拟请求和/或交叉无效，基于接口事件设置两个构建日期和两个到期日期，扩充专用高速缓存层级中可用的所有数据，其中多处理器一致性不是 观察缓存层次结构是否已将数据返回给处理器，其过期日期早于之前使用的所有数据的最新构建日期。 此外，描述了执行所述方法的单个处理器模型和计算机程序产品。
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公开(公告)号：US20100030968A1
公开(公告)日：2010-02-04
申请号：US12184165
申请日：2008-07-31
申请人： Eberhard Pasch , Hans-Werner Tast , Achim Haessler , Markus Nosse , Elmar Zipp
发明人： Eberhard Pasch , Hans-Werner Tast , Achim Haessler , Markus Nosse , Elmar Zipp
IPC分类号： G06F12/08
CPC分类号： G06F12/0261 , G06F12/0802
摘要： A computer implemented method of cache bounded reference counting for computer languages having automated memory management in which, for example, a reference to an object “Z” initially stored in an object “O” is fetched and the cache hardware is queried whether the reference to the object “Z” is a valid reference, is in the cache, and has a continuity flag set to “on”. If so, the object “O” is locked for an update, a reference counter is decremented for the object “Z” if the object “Z” resides in the cache, and a return code is set to zero to indicate that the object “Z” is de-referenced and that its storage memory can be released and re-used if the reference counter for the object “Z” reaches zero. Thereafter, the cache hardware is similarly queried regarding an object “N” that will become a new reference of object “O”.
摘要翻译： 具有自动存储器管理的计算机语言的高速缓存有界引用计数的计算机实现方法，其中例如对最初存储在对象“O”中的对象“Z”的引用被查询，并且查询高速缓存硬件是否被引用 对象“Z”是有效的引用，位于缓存中，并具有设置为“开”的连续性标志。 如果是这样，对象“O”被锁定以进行更新，如果对象“Z”驻留在高速缓存中，对象“Z”的引用计数器递减，并且将返回码设置为零以指示对象“ Z“被取消引用，并且如果对象”Z“的引用计数器达到零，则可以将其存储器释放并重新使用。 此后，对于将成为对象“O”的新引用的对象“N”，类似地查询高速缓存硬件。
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公开(公告)号：US20070011220A1
公开(公告)日：2007-01-11
申请号：US11390791
申请日：2006-03-28
IPC分类号： G06F17/15
CPC分类号： G06F7/766
摘要： A crossbar (20) circuit with multiplexer (22A, 22B) circuits implemented in a polygonal form on a chip. The crossbar can be used for implementing a permutation of input bits (24A, 24B) controlled by a bit vector (25). Horizontal and vertical wiring lengths in the crossbar (20) are reduced by stacking the operand latches (24A, 24B, 25) and horizontal or vertical multiplexers (22A, 22B). This implementation decreases the latency of the crossbar and avoids latches to store intermediated results, thus reducing area and power consumption.
摘要翻译： 具有以多边形形式在芯片上实现的多路复用器（22A，22B）电路的交叉开关（20）电路。 交叉开关可用于实现由位向量（25）控制的输入位（24A，24B）的置换。 通过堆叠操作数锁存器（24A，24B，25）和水平或垂直多路复用器（22A，22B）来减小横杆（20）中的水平和垂直布线长度。 该实现降低了交叉开关的延迟，并避免了锁存器来存储中间结果，从而减少了面积和功耗。
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10.发明授权公开(公告)号：US06968476B2
公开(公告)日：2005-11-22
申请号：US10180385
申请日：2002-06-26
CPC分类号： G06F9/3842 , G06F9/30174 , G06F9/3834 , G06F9/3863 , G06F9/3885
摘要： The present invention relates to data processing systems with built-in error recovery from a given checkpoint. In order to checkpoint more than one instruction per cycle it is proposed to collect updates of a predetermined maximum number of register contents performed by a respective plurality of CISC/RISC instructions in a buffer (CSB)(60) for checkpoint states, whereby a checkpoint state comprises as many buffer slots as registers can be updated by said plurality of CISC instructions and an entry for a Program Counter value associated with the youngest external instruction of said plurality, and to update an Architected Register Array (ARA)(64) with freshly collected register data after determining that no error was detected in the register data after completion of said youngest external instruction of said plurality of external instructions. Handshake synchronization for consistent updates between storage in an L2-cache (66) via a Store Buffer (65) and an Architected Register Array (ARA) (64) is provided which is based on the youngest instruction ID (40) stored in the Checkpoint State Buffer (CSB) (60).
摘要翻译： 本发明涉及从给定检查点内置错误恢复的数据处理系统。 为了对每个周期的多于一个指令进行检查，建议收集用于检查点状态的缓冲器（CSB）（60）中的相应多个CISC / RISC指令执行的预定最大数量的寄存器内容的更新，由此检查点 状态包括与所述多个CISC指令相对应的寄存器可更新的缓冲器槽，以及与所述多个最小外部指令相关联的程序计数器值的条目，并且以新鲜的方式更新建筑物寄存器阵列（ARA）（64） 在完成所述多个外部指令的所述最小外部指令之后确定在所述寄存器数据中没有检测到错误之后，收集的寄存器数据。 提供握手同步，用于通过存储缓冲器（65）和架构化寄存器阵列（ARA）（64）存储在L2高速缓存（66）中的一致更新，其基于存储在检查点中的最年轻的指令ID（40） 状态缓冲区（CSB）（60）。
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