-
公开(公告)号：US08440534B2
公开(公告)日：2013-05-14
申请号：US13104474
申请日：2011-05-10
申请人： Uwe Griebenow , Jan Hoentschel , Kai Frohberg , Heike Berthold , Katrin Reiche , Frank Feustel , Kerstin Ruttloff
发明人： Uwe Griebenow , Jan Hoentschel , Kai Frohberg , Heike Berthold , Katrin Reiche , Frank Feustel , Kerstin Ruttloff
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/6656 , H01L21/26513 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/6653 , H01L29/7836
摘要： Different threshold voltages of transistors of the same conductivity type in a complex integrated circuit may be adjusted on the basis of different Miller capacitances, which may be accomplished by appropriately adapting a spacer width and/or performing a tilted extension implantation. Thus, efficient process strategies may be available to controllably adjust the Miller capacitance, thereby providing enhanced transistor performance of low threshold transistors while not unduly contributing to process complexity compared to conventional approaches in which threshold voltage values may be adjusted on the basis of complex halo and well doping regimes.
-
2.发明授权Method of creating a strained channel region in a transistor by deep implantation of strain-inducing species below the channel region 有权通过在通道区域下方深入植入应变诱导物质来在晶体管中产生应变通道区域的方法公开(公告)号：US08110487B2
公开(公告)日：2012-02-07
申请号：US12178206
申请日：2008-07-23
IPC分类号： H01L21/425
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/1054 , H01L29/7849 , H01L29/78684
摘要： By incorporating a carbon species below the channel region of a P-channel transistor prior to the formation of the gate electrode structure, an efficient strain-inducing mechanism may provided, thereby enhancing performance of P-channel transistors. The position and size of the strain-inducing region may be determined on the basis of an implantation mask and respective implantation parameters, thereby providing a high degree of compatibility with conventional techniques, since the strain-inducing region may be incorporated at an early manufacturing stage, directly to respective “large area” contact elements.
摘要翻译： 通过在形成栅电极结构之前在P沟道晶体管的沟道区域下方引入碳物质，可以提供有效的应变诱导机制，从而增强P沟道晶体管的性能。 应变诱导区域的位置和尺寸可以基于注入掩模和各自的注入参数来确定，从而提供与常规技术的高度的相容性，因为应变诱导区域可以在早期制造阶段结合 ，直接到各自的“大面积”接触元件。
-
3.发明申请METHOD OF CREATING A STRAINED CHANNEL REGION IN A TRANSISTOR BY DEEP IMPLANTATION OF STRAIN-INDUCING SPECIES BELOW THE CHANNEL REGION 有权通过下列方式创建晶体管中的应变通道区域：通道区域以下应变诱导物种的深层植入公开(公告)号：US20090194789A1
公开(公告)日：2009-08-06
申请号：US12178206
申请日：2008-07-23
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/1054 , H01L29/7849 , H01L29/78684
摘要： By incorporating a carbon species below the channel region of a P-channel transistor prior to the formation of the gate electrode structure, an efficient strain-inducing mechanism may provided, thereby enhancing performance of P-channel transistors. The position and size of the strain-inducing region may be determined on the basis of an implantation mask and respective implantation parameters, thereby providing a high degree of compatibility with conventional techniques, since the strain-inducing region may be incorporated at an early manufacturing stage, directly to respective “large area” contact elements.
摘要翻译： 通过在形成栅电极结构之前在P沟道晶体管的沟道区域下方引入碳物质，可以提供有效的应变诱导机制，从而增强P沟道晶体管的性能。 应变诱导区域的位置和尺寸可以基于注入掩模和各自的注入参数来确定，从而提供与常规技术的高度的相容性，因为应变诱导区域可以在早期制造阶段结合 ，直接到各自的“大面积”接触元件。
-
4.发明申请THRESHOLD ADJUSTMENT FOR MOS DEVICES BY ADAPTING A SPACER WIDTH PRIOR TO IMPLANTATION 有权通过在植入前适应间隔宽度的MOS器件进行阈值调整公开(公告)号：US20110223732A1
公开(公告)日：2011-09-15
申请号：US13104474
申请日：2011-05-10
申请人： Uwe Griebenow , Jan Hoentschel , Kai Frohberg , Heike Berthold , Katrin Reiche , Frank Feustel , Kerstin Ruttloff
发明人： Uwe Griebenow , Jan Hoentschel , Kai Frohberg , Heike Berthold , Katrin Reiche , Frank Feustel , Kerstin Ruttloff
IPC分类号： H01L21/8234
CPC分类号： H01L29/6656 , H01L21/26513 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/6653 , H01L29/7836
摘要： Different threshold voltages of transistors of the same conductivity type in a complex integrated circuit may be adjusted on the basis of different Miller capacitances, which may be accomplished by appropriately adapting a spacer width and/or performing a tilted extension implantation. Thus, efficient process strategies may be available to controllably adjust the Miller capacitance, thereby providing enhanced transistor performance of low threshold transistors while not unduly contributing to process complexity compared to conventional approaches in which threshold voltage values may be adjusted on the basis of complex halo and well doping regimes.
摘要翻译： 可以基于不同的米勒电容来调整复合集成电路中相同导电类型的晶体管的不同阈值电压，这可以通过适当地适配间隔物宽度和/或执行倾斜延伸植入来实现。 因此，有效的处理策略可用于可控地调整米勒电容，从而提供低阈值晶体管的增强的晶体管性能，而不是过度复杂的工艺复杂性与常规方法相比，其中阈值电压值可以基于复数晕和 良好的兴奋剂制度。
-
5.发明申请Threshold adjustment for MOS devices by adapting a spacer width prior to implantation 审中-公开通过在植入之前调整间隔物宽度来调整MOS器件的阈值公开(公告)号：US20090321850A1
公开(公告)日：2009-12-31
申请号：US12413765
申请日：2009-03-30
申请人： Uwe Griebenow , Jan Hoentschel , Kai Frohberg , Heike Berthold , Katrin Reiche , Frank Feustel , Kerstin Ruttloff
发明人： Uwe Griebenow , Jan Hoentschel , Kai Frohberg , Heike Berthold , Katrin Reiche , Frank Feustel , Kerstin Ruttloff
IPC分类号： H01L27/088 , H01L21/8236
CPC分类号： H01L21/26513 , H01L21/26506 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/6653 , H01L29/6656 , H01L29/7836
摘要： Different threshold voltages of transistors of the same conductivity type in a complex integrated circuit may be adjusted on the basis of different Miller capacitances, which may be accomplished by appropriately adapting a spacer width and/or performing a tilted extension implantation. Thus, efficient process strategies may be available to controllably adjust the Miller capacitance, thereby providing enhanced transistor performance of low threshold transistors while not unduly contributing to process complexity compared to conventional approaches in which threshold voltage values may be adjusted on the basis of complex halo and well doping regimes.
摘要翻译： 可以基于不同的米勒电容来调整复合集成电路中相同导电类型的晶体管的不同阈值电压，这可以通过适当地适配间隔物宽度和/或执行倾斜延伸植入来实现。 因此，有效的处理策略可用于可控地调整米勒电容，从而提供低阈值晶体管的增强的晶体管性能，而不是过度复杂的工艺复杂性与常规方法相比，其中阈值电压值可以基于复数晕和 良好的兴奋剂制度。
-
6.发明申请TECHNIQUE FOR REDUCING SILICIDE NON-UNIFORMITIES IN POLYSILICON GATE ELECTRODES BY AN INTERMEDIATE DIFFUSION BLOCKING LAYER 审中-公开通过中间扩散阻挡层减少多晶硅栅极中硅化物非均质的技术公开(公告)号：US20100025782A1
公开(公告)日：2010-02-04
申请号：US12464917
申请日：2009-05-13
申请人： Uwe Griebenow , Kai Frohberg , Kerstin Ruttloff
发明人： Uwe Griebenow , Kai Frohberg , Kerstin Ruttloff
CPC分类号： H01L21/28052 , H01L29/4933 , H01L29/66507 , H01L29/6659 , H01L29/7833
摘要： Threshold variability in advanced transistor elements, as well as increased leakage currents, may be reduced by incorporating a barrier material in a polysilicon gate electrode. The barrier material results in a well-controllable and well-defined metal silicide in the polysilicon gate electrode during the silicidation sequence and during the further processing by significantly reducing the diffusion of a metal species, such as nickel, into the vicinity of the gate dielectric material.
摘要翻译： 可以通过在多晶硅栅电极中并入阻挡材料来降低高级晶体管元件的阈值变化以及增加的漏电流。 阻挡材料在硅化顺序期间在多晶硅栅极电极中形成良好可控且良好限定的金属硅化物，并且在进一步处理期间，通过显着地减少诸如镍的金属物质扩散到栅极电介质附近 材料。
-
7.发明申请DRIVE CURRENT ADJUSTMENT FOR TRANSISTORS FORMED IN THE SAME ACTIVE REGION BY LOCALLY INDUCING DIFFERENT LATERAL STRAIN LEVELS IN THE ACTIVE REGION 审中-公开通过局部诱导活跃区域中不同的侧向应变水平在同一活跃区域形成的晶体管的驱动电流调整公开(公告)号：US20090294868A1
公开(公告)日：2009-12-03
申请号：US12424095
申请日：2009-04-15
申请人： Uwe Griebenow , Kai Frohberg , Kerstin Ruttloff , Katrin Reiche
发明人： Uwe Griebenow , Kai Frohberg , Kerstin Ruttloff , Katrin Reiche
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823412 , H01L21/823425 , H01L21/823807 , H01L29/7843
摘要： The drive current capability of a pull-down transistor and a pass transistor formed in a common active region may be adjusted on the basis of a strain-inducing mechanism, such as a stressed dielectric material and a stress memorization technique, thereby providing a simplified overall geometric configuration of the active region. Hence, static RAM cells may be formed on the basis of a minimum channel length with a simplified configuration of the active region, thereby avoiding significant yield losses as may be observed in sophisticated devices in which a pronounced variation of the transistor width may be used to adjust the ratio of the drive current capabilities for the pull-down transistor and the pass transistor.
摘要翻译： 形成在公共有源区域中的下拉晶体管和传输晶体管的驱动电流能力可以基于诸如应力介电材料和应力记忆技术之类的应变诱导机构来调节，从而提供简化的总体 活动区域的几何配置。 因此，可以基于具有有源区域的简化配置的最小沟道长度形成静态RAM单元，从而避免了在可以使用晶体管宽度的显着变化的复杂器件中可观察到的显着的产量损失 调整下拉晶体管和传输晶体管的驱动电流能力的比值。
-
8.发明授权SOI semiconductor device comprising substrate diodes having a topography tolerant contact structure 有权SOI半导体器件包括具有地形容忍接触结构的衬底二极管公开(公告)号：US08436425B2
公开(公告)日：2013-05-07
申请号：US12915168
申请日：2010-10-29
申请人： Jens Heinrich , Kai Frohberg , Kerstin Ruttloff
发明人： Jens Heinrich , Kai Frohberg , Kerstin Ruttloff
IPC分类号： H01L27/12
CPC分类号： H01L29/8611 , H01L27/0207 , H01L27/0629 , H01L27/1207
摘要： In an SOI semiconductor device, substrate diodes may be formed on the basis of a superior design of the contact level and the metallization layer, thereby avoiding the presence of metal lines connecting to both diode electrodes in the critical substrate diode area. To this end, contact trenches may be provided so as to locally connect one type of diode electrodes within the contact level. Consequently, additional process steps for planarizing the surface topography upon forming the contact level may be avoided.
摘要翻译： 在SOI半导体器件中，可以基于接触电平和金属化层的优良设计来形成衬底二极管，从而避免在关键衬底二极管区域中存在连接到二极管电极的金属线。 为此，可以提供接触沟槽，以便在接触电平内局部连接一种类型的二极管电极。 因此，可以避免在形成接触电平时使表面形貌平坦化的附加工艺步骤。
-
9.发明授权Contacts and vias of a semiconductor device formed by a hard mask and double exposure 有权通过硬掩模和双重曝光形成的半导体器件的触点和通孔公开(公告)号：US08318598B2
公开(公告)日：2012-11-27
申请号：US12537321
申请日：2009-08-07
申请人： Sven Beyer , Kai Frohberg , Katrin Reiche , Kerstin Ruttloff
发明人： Sven Beyer , Kai Frohberg , Katrin Reiche , Kerstin Ruttloff
IPC分类号： H01L21/4763
CPC分类号： H01L21/31144 , H01L21/76816 , H01L21/76897
摘要： A contact element may be formed on the basis of a hard mask, which may be patterned on the basis of a first resist mask and on the basis of a second resist mask, to define an appropriate intersection area which may represent the final design dimensions of the contact element. Consequently, each of the resist masks may be formed on the basis of a photolithography process with less restrictive constraints, since at least one of the lateral dimensions may be selected as a non-critical dimension in each of the two resist masks.
摘要翻译： 可以基于硬掩模形成接触元件，硬掩模可以基于第一抗蚀剂掩模并且基于第二抗蚀剂掩模来图案化，以限定适当的交叉区域，其可以表示最终的设计尺寸 接触元件。 因此，可以基于具有较少限制性约束的光刻工艺来形成每个抗蚀剂掩模，因为在两个抗蚀剂掩模中的每一个中可以选择至少一个横向尺寸作为非临界尺寸。
-
10.发明授权SOI semiconductor device with reduced topography above a substrate window area 有权SOI衬底窗口区域上方的图形减小的SOI半导体器件公开(公告)号：US08048726B2
公开(公告)日：2011-11-01
申请号：US12914663
申请日：2010-10-28
申请人： Jens Heinrich , Kai Frohberg , Sven Mueller , Kerstin Ruttloff
发明人： Jens Heinrich , Kai Frohberg , Sven Mueller , Kerstin Ruttloff
IPC分类号： H01L21/00 , H01L21/84 , H01L21/302 , H01L21/461
CPC分类号： H01L21/84 , H01L27/1207
摘要： In sophisticated SOI devices, circuit elements, such as substrate diodes, may be formed in the crystalline substrate material on the basis of a substrate window, wherein the pronounced surface topography may be compensated for or at least reduced by performing additional planarization processes, such as the deposition of a planarization material, and a subsequent etch process when forming the contact level of the semiconductor device.
摘要翻译： 在复杂的SOI器件中，可以在衬底窗口的基础上在晶体衬底材料中形成诸如衬底二极管之类的电路元件，其中可以通过执行附加的平坦化工艺来补偿或至少减少显着的表面形貌，例如 平坦化材料的沉积，以及当形成半导体器件的接触电平时的后续蚀刻工艺。
-
-
-
-
-
-
-
-
-
搜索结果
27 条记录 (耗时 0.022 秒)
