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    Contacts and vias of a semiconductor device formed by a hard mask and double exposure
    1.
    发明授权
    Contacts and vias of a semiconductor device formed by a hard mask and double exposure 有权
    通过硬掩模和双重曝光形成的半导体器件的触点和通孔

    公开(公告)号：US08318598B2

    公开(公告)日：2012-11-27

    申请号：US12537321

    申请日：2009-08-07

    申请人： Sven Beyer ,  Kai Frohberg ,  Katrin Reiche ,  Kerstin Ruttloff

    发明人： Sven Beyer ,  Kai Frohberg ,  Katrin Reiche ,  Kerstin Ruttloff

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/31144 ,  H01L21/76816 ,  H01L21/76897

    摘要： A contact element may be formed on the basis of a hard mask, which may be patterned on the basis of a first resist mask and on the basis of a second resist mask, to define an appropriate intersection area which may represent the final design dimensions of the contact element. Consequently, each of the resist masks may be formed on the basis of a photolithography process with less restrictive constraints, since at least one of the lateral dimensions may be selected as a non-critical dimension in each of the two resist masks.

    摘要翻译： 可以基于硬掩模形成接触元件，硬掩模可以基于第一抗蚀剂掩模并且基于第二抗蚀剂掩模来图案化，以限定适当的交叉区域，其可以表示最终的设计尺寸 接触元件。 因此，可以基于具有较少限制性约束的光刻工艺来形成每个抗蚀剂掩模，因为在两个抗蚀剂掩模中的每一个中可以选择至少一个横向尺寸作为非临界尺寸。

    CONTACTS AND VIAS OF A SEMICONDUCTOR DEVICE FORMED BY A HARD MASK AND DOUBLE EXPOSURE
    2.
    发明申请
    CONTACTS AND VIAS OF A SEMICONDUCTOR DEVICE FORMED BY A HARD MASK AND DOUBLE EXPOSURE 有权
    通过硬掩模和双重暴露形成的半导体器件的接触和孔

    公开(公告)号：US20100078823A1

    公开(公告)日：2010-04-01

    申请号：US12537321

    申请日：2009-08-07

    申请人： Sven Beyer ,  Kai Frohberg ,  Katrin Reiche ,  Kerstin Ruttloff

    发明人： Sven Beyer ,  Kai Frohberg ,  Katrin Reiche ,  Kerstin Ruttloff

    IPC分类号： H01L23/522 ,  H01L21/306

    CPC分类号： H01L21/31144 ,  H01L21/76816 ,  H01L21/76897

    摘要： A contact element may be formed on the basis of a hard mask, which may be patterned on the basis of a first resist mask and on the basis of a second resist mask, to define an appropriate intersection area which may represent the final design dimensions of the contact element. Consequently, each of the resist masks may be formed on the basis of a photolithography process with less restrictive constraints, since at least one of the lateral dimensions may be selected as a non-critical dimension in each of the two resist masks.

    摘要翻译： 可以基于硬掩模形成接触元件，硬掩模可以基于第一抗蚀剂掩模并且基于第二抗蚀剂掩模来图案化，以限定适当的交叉区域，其可以表示最终的设计尺寸 接触元件。 因此，可以基于具有较少限制性约束的光刻工艺来形成每个抗蚀剂掩模，因为在两个抗蚀剂掩模中的每一个中可以选择至少一个横向尺寸作为非临界尺寸。

    High-K metal gate electrode structures formed by early cap layer adaptation
    3.
    发明授权
    High-K metal gate electrode structures formed by early cap layer adaptation 有权
    通过早期盖层适应形成的高K金属栅电极结构

    公开(公告)号：US08664057B2

    公开(公告)日：2014-03-04

    申请号：US13565970

    申请日：2012-08-03

    申请人： Rohit Pal ,  Sven Beyer ,  Andy Wei ,  Richard Carter

    发明人： Rohit Pal ,  Sven Beyer ,  Andy Wei ,  Richard Carter

    IPC分类号： H01L21/8238 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/336 ,  H01L21/28 ,  H01L21/44 ,  H01L21/8234

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823828

    摘要： When forming high-k metal gate electrode structures in transistors of different conductivity type while also incorporating an embedded strain-inducing semiconductor alloy selectively in one type of transistor, superior process uniformity may be accomplished by selectively reducing the thickness of a dielectric cap material of a gate layer stack above the active region of transistors which do not receive the strain-inducing semiconductor alloy. In this case, superior confinement and thus integrity of sensitive gate materials may be accomplished in process strategies in which the sophisticated high-k metal gate electrode structures are formed in an early manufacturing stage, while, in a replacement gate approach, superior process uniformity is achieved upon exposing the surface of a placeholder electrode material.

    摘要翻译： 当在不同导电类型的晶体管中形成高k金属栅极电极结构时，同时在一种类型的晶体管中选择性地并入嵌入式应变诱导半导体合金，可以通过选择性地减小介电帽材料的厚度来实现优异的工艺均匀性 栅极层堆叠在不接收应变诱导半导体合金的晶体管的有源区上方。 在这种情况下，可以在早期制造阶段中形成复杂的高k金属栅极电极结构的工艺策略中实现优异的限制和因此敏感栅极材料的完整性，而在替代栅极方法中，优良的工艺均匀性是 在暴露观察者电极材料的表面时实现。

    Performance enhancement in PFET transistors comprising high-k metal gate stack by increasing dopant confinement
    4.
    发明授权
    Performance enhancement in PFET transistors comprising high-k metal gate stack by increasing dopant confinement 有权
    通过增加掺杂剂约束，包括高k金属栅极堆叠的PFET晶体管的性能增强

    公开(公告)号：US08404550B2

    公开(公告)日：2013-03-26

    申请号：US12905383

    申请日：2010-10-15

    申请人： Thilo Scheiper ,  Sven Beyer ,  Andy Wei ,  Jan Hoentschel

    发明人： Thilo Scheiper ,  Sven Beyer ,  Andy Wei ,  Jan Hoentschel

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7848 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66651

    摘要： In a P-channel transistor comprising a high-k metal gate electrode structure, a superior dopant profile may be obtained, at least in the threshold adjusting semiconductor material, such as a silicon/germanium material, by incorporating a diffusion blocking species, such as fluorine, prior to forming the threshold adjusting semiconductor material. Consequently, the drain and source extension regions may be provided with a high dopant concentration as required for obtaining the target Miller capacitance without inducing undue dopant diffusion below the threshold adjusting semiconductor material, which may otherwise result in increased leakage currents and increased risk of punch through events.

    摘要翻译： 在包含高k金属栅电极结构的P沟道晶体管中，至少在阈值调节半导体材料（例如硅/锗材料）中可以通过掺入扩散阻挡物质获得优异的掺杂剂分布，例如 在形成阈值调节半导体材料之前。 因此，漏极和源极延伸区域可以被提供有高的掺杂剂浓度，以获得目标米勒电容，而不会导致低于阈值调节半导体材料的不适当的掺杂剂扩散，否则可能导致增加的漏电流和增加的穿孔风险 事件

    Dual Cavity Etch for Embedded Stressor Regions
    5.
    发明申请
    Dual Cavity Etch for Embedded Stressor Regions 审中-公开
    嵌入式应力区域的双腔蚀刻

    公开(公告)号：US20120292637A1

    公开(公告)日：2012-11-22

    申请号：US13109134

    申请日：2011-05-17

    申请人： Sven Beyer ,  Peter Baars ,  Jan Hoentschel ,  Thilo Scheiper

    发明人： Sven Beyer ,  Peter Baars ,  Jan Hoentschel ,  Thilo Scheiper

    IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/20

    CPC分类号： H01L21/823807 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

    摘要： Generally, the present disclosure is directed to methods for forming embedded stressor regions in semiconductor devices such as transistor elements and the like. One illustrative method disclosed herein includes forming a first material in first cavities formed in a first active area adjacent to a first channel region of a semiconductor device, wherein the first material induces a first stress in the first channel region. The method also includes, among other things, forming a second material in second cavities formed in a second active area adjacent to a second channel region of the semiconductor device, wherein the second material induces a second stress in the second channel region that is of an opposite type of the first stress in the first channel region, and wherein the first and second cavities are formed during a common etch process.

    摘要翻译： 通常，本公开涉及在诸如晶体管元件等的半导体器件中形成嵌入的应力源区域的方法。 本文公开的一种说明性方法包括在与半导体器件的第一沟道区相邻的第一有源区中形成的第一空腔中形成第一材料，其中第一材料在第一沟道区域中引起第一应力。 该方法还包括在形成在与半导体器件的第二沟道区相邻的第二有源区中的第二腔中形成第二材料，其中第二材料在第二沟道区域中引起第二应力 在第一通道区域中相反类型的第一应力，并且其中第一和第二空腔在公共蚀刻工艺期间形成。

    WORK FUNCTION ADJUSTMENT IN HIGH-K GATE STACKS FOR DEVICES OF DIFFERENT THRESHOLD VOLTAGE
    10.
    发明申请
    WORK FUNCTION ADJUSTMENT IN HIGH-K GATE STACKS FOR DEVICES OF DIFFERENT THRESHOLD VOLTAGE 有权
    用于不同阈值电压器件的高K栅极堆栈中的工作功能调整

    公开(公告)号：US20110127616A1

    公开(公告)日：2011-06-02

    申请号：US12905501

    申请日：2010-10-15

    申请人： Jan Hoentschel ,  Sven Beyer ,  Thilo Scheiper

    发明人： Jan Hoentschel ,  Sven Beyer ,  Thilo Scheiper

    IPC分类号： H01L27/088 ,  H01L21/336

    CPC分类号： H01L21/28176 ,  H01L21/823857 ,  H01L29/517

    摘要： In sophisticated semiconductor devices, different threshold voltage levels for transistors may be set in an early manufacturing stage, i.e., prior to patterning the gate electrode structures, by using multiple diffusion processes and/or gate dielectric materials. In this manner, substantially the same gate layer stacks, i.e., the same electrode materials and the same dielectric cap materials, may be used, thereby providing superior patterning uniformity when applying sophisticated etch strategies.

    摘要翻译： 在复杂的半导体器件中，可以在早期制造阶段，即在通过使用多个扩散工艺和/或栅极电介质材料图案化栅极电极结构之前，将晶体管的不同阈值电压电平设置。 以这种方式，可以使用基本相同的栅极层堆叠，即相同的电极材料和相同的电介质盖材料，从而在应用复杂的蚀刻策略时提供优异的图案均匀性。