公开(公告)号：US20040105955A1

公开(公告)日：2004-06-03

申请号：US10717116

申请日：2003-11-19

申请人： VIA TECHNOLOGIES, INC.

发明人： Kwun Yao Ho ,  Moriss Kung

IPC分类号： B32B003/06

CPC分类号： H05K3/4617 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48228 ,  H01L2224/48464 ,  H01L2924/3011 ,  H05K3/062 ,  H05K3/064 ,  H05K3/423 ,  H05K3/4602 ,  H05K3/4647 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/09881 ,  H05K2203/0384 ,  H05K2203/0733 ,  Y10S428/901 ,  Y10T428/24025 ,  Y10T428/24917 ,  H01L2924/00014 ,  H01L2924/00

摘要： A lamination process and structure of a high layout density substrate is disclosed. The lamination process comprises the following steps. First of all, a plurality of laminating layers are individually formed, wherein each laminating layer has a first dielectric layer, a plurality of first vias and a patterned conducting layer. Next, a bottom layer having a second dielectric layer and a plurality of second vias is formed. Then, the laminating layers and the bottom layer are stacked. Finally, the laminating layers and the bottom layer are laminated simultaneously to form a multiplayer substrate at one time.

摘要翻译： 公开了一种高布局密度衬底的叠层工艺和结构。 层压方法包括以下步骤。 首先，分别形成多个层压层，其中每个层压层具有第一介电层，多个第一通孔和图案化的导电层。 接下来，形成具有第二电介质层和多个第二通孔的底层。 然后层叠层叠体和底层。 最后，层压层和底层同时层压以形成多层底板。

公开(公告)号：US20040124513A1

公开(公告)日：2004-07-01

申请号：US10734195

申请日：2003-12-15

申请人： VIA Technologies, Inc.

发明人： Kwun Yao Ho ,  Moriss Kung

IPC分类号： H01L021/44 ,  H01L023/02 ,  H01L029/40

CPC分类号： H01L23/5385 ,  H01L23/147 ,  H01L23/5384 ,  H01L25/0652 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05684

摘要： The invention discloses a high-density multi-chip module package which can integrates active and passive devices stacked by a three-dimensional face-to-back interconnection. The multichip module package of the invention at least comprises a multichip module substrate which has an semiconductor substrate, an insulating layer on the semiconductor substrate, a multilayer interconnection structure on the insulating layer, and a plurality of conductive plugs penetrating the semiconductor substrate and the insulating layer to provide electric connection with the multilayer interconnection structure; and a plurality of chips disposing on the semiconductor substrate and electrically connecting to the multilayer interconnection structure through the conductive plugs.

摘要翻译： 本发明公开了一种高密度多芯片模块封装，可以集成通过三维面对面互连堆叠的有源和无源器件。 本发明的多芯片模块封装至少包括多芯片模块基板，其具有半导体衬底，半导体衬底上的绝缘层，绝缘层上的多层互连结构，以及穿透半导体衬底和绝缘层的多个导电插塞 层，以提供与多层互连结构的电连接; 以及设置在半导体基板上并通过导电插塞电连接到多层互连结构的多个芯片。