公开(公告)号：US20130222020A1

公开(公告)日：2013-08-29

申请号：US13850666

申请日：2013-03-26

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Yeong-Sheng LEE

IPC: H03L7/14

CPC classification number: H03L7/14 ,  H03L7/0816 ,  H03L7/0891 ,  H03L7/099 ,  H04L27/00

Abstract: A signal generation device is provided to generate an output signal with constant frequency. The signal generation device includes a frequency-control circuit and a voltage-controlled delay line. The frequency-control circuit includes a pulse generator, generating a reference pulse signal according to a transition of the reference signal and a comparison pulse signal according to a transition of the comparison result signal, to re-shape the reference signal and the comparison result signal into narrow pulses suitable for clocking and resetting flip-flops.

Abstract translation: 提供信号发生装置以产生具有恒定频率的输出信号。 信号发生装置包括频率控制电路和电压控制延迟线。 频率控制电路包括脉冲发生器，根据比较结果信号的转变，根据参考信号的转变和比较脉冲信号产生参考脉冲信号，以重新形成参考信号和比较结果信号 转换成适合时钟和复位触发器的窄脉冲。

公开(公告)号：US20150207497A1

公开(公告)日：2015-07-23

申请号：US14159191

申请日：2014-01-20

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Yeong-Sheng LEE

IPC: H03K5/003 ,  H03F3/45

CPC classification number: H03K5/003 ,  G05F3/30 ,  H03F3/45475 ,  H03F3/45982 ,  H03F2203/45212

Abstract: A low-offset bandgap circuit including a core bandgap circuit and an offset-cancelling circuit is provided. The low-offset bandgap circuit provides a reference voltage at an output node. The core bandgap circuit includes a core operational amplifier to generate a core current. The offset-cancelling circuit is coupled to two input terminals of the core operational amplifier. The offset-cancelling circuit is configured to generate a compensation current according to the voltages at the two input terminals of the core operational amplifier so as to compensate for an offset voltage of the core operational amplifier. The reference voltage is generated according to the core current and the compensation current.

Abstract translation: 提供了一种包括内核带隙电路和偏移消除电路的低偏移带隙电路。 低偏移带隙电路在输出节点处提供参考电压。 核心带隙电路包括用于产生核心电流的核心运算放大器。 偏移消除电路耦合到核心运算放大器的两个输入端。 偏移消除电路被配置为根据核心运算放大器的两个输入端处的电压产生补偿电流，以补偿核心运算放大器的偏移电压。 参考电压根据磁芯电流和补偿电流产生。

公开(公告)号：US20130076404A1

公开(公告)日：2013-03-28

申请号：US13685131

申请日：2012-11-26

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Yeong-Sheng LEE ,  Kuen-Chir WANG

IPC: H03K17/04 ,  H03K17/00

CPC classification number: H03K17/04 ,  H03K17/002 ,  H03K19/018528 ,  H04L25/0272 ,  H04L25/0278

Abstract: A low voltage differential signal driving circuit including positive and negative differential output terminals, an automatic level selector, an output level detector and a transition accelerator. The positive and negative differential output terminals provide a transmission interface with a differential output signal for transmission of a data signal. The automatic level selector outputs a reference voltage corresponding to the transmission interface. The output level detector generates a low-high (or high-low) transition acceleration control signal based on the data signal, the reference voltage, and VTXP signal at the positive differential output terminal (or VTXN signal at the negative differential output terminal). In accordance with the low-high (or high-low) transition acceleration control signal, the transition accelerator couples the positive (or negative) differential output terminal to a high voltage source and couples the negative (or positive) differential output terminal to a low voltage source to accelerate transition of the differential output signal.

Abstract translation: 包括正和负差分输出端子的低电压差分信号驱动电路，自动电平选择器，输出电平检测器和转换加速器。 正和负差分输出端子提供具有用于传输数据信号的差分输出信号的传输接口。 自动电平选择器输出与传输接口对应的参考电压。 输出电平检测器基于正差分输出端子（或负差分输出端子处的VTXN信号）的数据信号，参考电压和VTXP信号产生低电平（或高 - 低）转换加速控制信号。 根据低 - 高（或高 - 低）转换加速度控制信号，转换加速器将正（或负）差分输出端耦合到高电压源，并将负（或正）差分输出端耦合到低电平 电压源加速差分输出信号的转换。

公开(公告)号：US20140203865A1

公开(公告)日：2014-07-24

申请号：US13745991

申请日：2013-01-21

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Yeong-Sheng LEE

IPC: G05F3/24

CPC classification number: G05F3/24

Abstract: An output buffer is provided. The output buffer is coupled to a first voltage source providing a first supply voltage and used for generating an output signal at an output terminal according to an input signal. The output buffer includes first and second transistors and a self-bias circuit. The first and second transistors are cascaded between the output terminal and a reference voltage. The self-bias circuit is coupled to the output terminal and the control electrode of the first transistor. When the output buffer does not receive the first supply voltage, the self-bias circuit provides a first bias voltage to the control electrode of the first transistor according to the output signal to decrease voltage differences between the control electrode and the input and output electrodes of the first transistor to be lower than a predetermined voltage.

Abstract translation: 提供输出缓冲区。 输出缓冲器耦合到提供第一电源电压并用于根据输入信号在输出端产生输出信号的第一电压源。 输出缓冲器包括第一和第二晶体管和自偏置电路。 第一和第二晶体管级联在输出端和参考电压之间。 自偏置电路耦合到第一晶体管的输出端和控制电极。 当输出缓冲器没有接收到第一电源电压时，自偏置电路根据输出信号向第一晶体管的控制电极提供第一偏置电压，以减小控制电极与输入和输出电极之间的电压差 第一晶体管低于预定电压。

公开(公告)号：US20130300511A1

公开(公告)日：2013-11-14

申请号：US13943174

申请日：2013-07-16

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Yeong-Sheng LEE

IPC: H03B1/00

CPC classification number: H03B1/00 ,  H03K3/0322

Abstract: A voltage controlled oscillator generating an oscillation signal according to a first control signal without a silent region. The voltage controlled oscillator includes a control signal adjuster and a plurality of delay cells. The control signal adjuster receives the first control signal and generates a second and a third control signal according to the first control signal. The voltage level of the third control signal is higher than that of the second control signal and the voltage level of the second control signal is higher than that of the first control signal. The plurality of delay cells are ring-connected and controlled by the first, the second, and the third control signals to generate the oscillation signal. Each delay cell includes three sets of current generation transistors. The three sets of current generation transistors are separately controlled by the three different control signals.

Abstract translation: 压控振荡器根据没有静音区域的第一控制信号产生振荡信号。 压控振荡器包括控制信号调节器和多个延迟单元。 控制信号调节器接收第一控制信号，并根据第一控制信号产生第二和第三控制信号。 第三控制信号的电压电平高于第二控制信号的电压电平，第二控制信号的电压电平高于第一控制信号的电压电平。 多个延迟单元由第一，第二和第三控制信号环形连接和控制，以产生振荡信号。 每个延迟单元包括三组电流产生晶体管。 三组电流发生晶体管由三种不同的控制信号分别控制。

公开(公告)号：US20130099840A1

公开(公告)日：2013-04-25

申请号：US13644403

申请日：2012-10-04

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Yeong-Sheng LEE ,  Kuen-Chir WANG

IPC: H03K3/017

CPC classification number: H02M3/156

Abstract: A duty adjustment circuit is provided. The duty adjustment circuit is used to adjust a duty cycle of a first driving signal. The duty adjustment circuit includes a filter, a first comparator, and a first duty adjustor. The filter receives a comparison result signal and filters the comparison result signal to generate a duty information signal. The duty information signal indicates a duty cycle of the comparison result signal. The first comparator receives the duty information signal and determines whether a direct-current (DC) level of the duty information signal falls into a predefined voltage range to generate a first adjustment signal. The first duty adjustor receives the first adjustment signal and the first driving signal and adjusts the duty cycle of the first driving signal according to the first adjustment signal.

Abstract translation: 提供了一个占空比调整电路。 占空比调整电路用于调整第一驱动信号的占空比。 占空比调节电路包括滤波器，第一比较器和第一占空比调节器。 滤波器接收比较结果信号并对比较结果信号进行滤波以产生占空比信息信号。 占空信息信号表示比较结果信号的占空比。 第一比较器接收占空信息信号，并确定占空比信息信号的直流（DC）电平是否落入预定的电压范围以产生第一调整信号。 第一负载调节器接收第一调整信号和第一驱动信号，并根据第一调整信号调整第一驱动信号的占空比。