公开(公告)号：US20150193308A1

公开(公告)日：2015-07-09

申请号：US14561612

申请日：2014-12-05

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Yao-Shun HUNG ,  Chin-Yin TSAI ,  Yi-Lin LAI

IPC: G06F11/14 ,  G06F11/07 ,  G06F9/44

CPC classification number: G06F3/0619 ,  G06F3/0632 ,  G06F3/064 ,  G06F3/0673 ,  G06F9/441 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/076 ,  G06F11/1076 ,  G06F11/1417

Abstract: A memory chip coupled to a host includes a memory and a controller. Multiple boot images having the same content are pre-loaded in the memory. The controller is coupled to the memory for processing data transmission between the memory chip and the host. The controller further determines whether the memory chip enters a boot mode for the first time. When the memory chip enters the boot mode for the first time, the controller accesses the memory so as to obtain a correct boot image from the boot images and transmits the correct boot image to the host.

Abstract translation: 耦合到主机的存储器芯片包括存储器和控制器。 具有相同内容的多个引导映像被预先加载到存储器中。 控制器耦合到存储器，用于处理存储器芯片和主机之间的数据传输。 控制器进一步确定存储器芯片是否首次进入引导模式。 当存储器芯片第一次进入引导模式时，控制器访问存储器，以从引导映像获得正确的引导映像，并将正确的引导映像传送到主机。

公开(公告)号：US20170038988A1

公开(公告)日：2017-02-09

申请号：US15333004

申请日：2016-10-24

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Yao-Shun HUNG ,  Chin-Yin TSAI ,  Yi-Lin LAI

IPC: G06F3/06 ,  G06F11/10 ,  G06F9/44

CPC classification number: G06F3/0619 ,  G06F3/0632 ,  G06F3/064 ,  G06F3/0673 ,  G06F9/441 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/076 ,  G06F11/1076 ,  G06F11/1417

Abstract: A memory chip coupled to a host includes a memory and a controller. The memory is pre-loaded with a plurality of boot images, wherein the boot images have the same content. The controller is coupled to the memory, and processes data transmissions between the memory chip and the host, wherein the controller further determines whether the memory chip enters a boot mode for the first time, and when the memory chip enters the boot mode for the first time, the controller accesses the memory to obtain a correct boot image from the boot images and transmits the correct boot image to the host. Further, each boot image includes a plurality of data blocks, and the controller loads a plurality of correct data blocks from one or more of the boot images to obtain the correct boot image.

Abstract translation: 耦合到主机的存储器芯片包括存储器和控制器。 存储器预加载有多个引导映像，其中引导映像具有相同的内容。 控制器耦合到存储器，并且处理存储器芯片和主机之间的数据传输，其中控制器进一步确定存储器芯片是否首次进入引导模式，以及当存储器芯片进入第一个引导模式时 时间，控制器访问内存以从引导映像获取正确的引导映像，并将正确的引导映像传输到主机。 此外，每个引导映像包括多个数据块，并且控制器从一个或多个引导映像加载多个正确的数据块以获得正确的启动映像。

公开(公告)号：US20150324283A1

公开(公告)日：2015-11-12

申请号：US14469703

申请日：2014-08-27

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Yi-Lin LAI

IPC: G06F12/02 ,  G11C29/42 ,  G11C29/52 ,  G06F11/10

CPC classification number: G06F3/06 ,  G06F11/1072 ,  G06F12/0246 ,  G06F12/06 ,  G06F2212/7201 ,  G11C29/42 ,  G11C29/52

Abstract: A flash memory control method, storing a logical-to-physical address mapping relationship between a host and a flash memory and a root table in the flash memory and providing a non-volatile storage area storing a root table pointer. A mapping relationship pointer is set forth in the root table to show where the logical-to-physical address mapping relationship is stored in the flash memory. The root table pointer points to the root table stored in the flash memory. In response to a power restoration request issued from the host, the flash memory is accessed based on the root table pointer and thereby the root table is read and the logical-to-physical address mapping relationship is retrieved from the flash memory based on the mapping relationship pointer set forth in the root table.

Abstract translation: 一种闪速存储器控制方法，存储主机与闪速存储器之间的逻辑到物理地址映射关系以及闪速存储器中的根表，并提供存储根表指针的非易失性存储区域。 映射关系指针在根表中列出，以显示逻辑到物理地址映射关系存储在闪存中的位置。 根表指针指向存储在闪存中的根表。 响应从主机发出的电源恢复请求，基于根表指针访问闪存，从而读取根表，并且基于映射从闪存中检索逻辑到物理地址映射关系 关系指针在根表中列出。

公开(公告)号：US20150309886A1

公开(公告)日：2015-10-29

申请号：US14514733

申请日：2014-10-15

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Chin-Yin TSAI ,  Yi-Lin LAI

IPC: G06F11/14 ,  G06F12/02

CPC classification number: G06F11/1469 ,  G06F11/1441 ,  G06F11/1451 ,  G06F12/0246 ,  G06F2201/84 ,  G06F2212/1008 ,  G06F2212/7201 ,  G06F2212/7207 ,  G06F2212/7209

Abstract: A flash memory control technique with high reliability is provided. A flash memory controller provides a volatile storage area for temporary storage of logical-to-physical address mapping data between a host and a flash memory as well as error detection codes encoded from the logical-to-physical address mapping data. When reading from the volatile storage area, the microcontroller of the flash memory controller is configured to perform an error detection procedure based on the error detection codes. The microcontroller is further configured to restore the logical-to-physical address mapping data in the volatile storage area based on a backup of the logical-to-physical address mapping data.

Abstract translation: 提供了高可靠性的闪存控制技术。 闪速存储器控制器提供用于临时存储主机和闪速存储器之间的逻辑到物理地址映射数据的易失性存储区域以及从逻辑到物理地址映射数据编码的错误检测代码。 当从易失性存储区读取时，闪存控制器的微控制器被配置为基于错误检测码执行错误检测过程。 微控制器还被配置为基于逻辑到物理地址映射数据的备份来恢复易失性存储区域中的逻辑到物理地址映射数据。

公开(公告)号：US20150089088A1

公开(公告)日：2015-03-26

申请号：US14452784

申请日：2014-08-06

Applicant: Via Technologies, Inc.

Inventor： Chia-Ying KUO ,  Yi-Lin LAI

IPC: G06F13/14 ,  G06F3/06

CPC classification number: G06F13/4086 ,  G06F13/20

Abstract: An interface controller coupling the main body of an external electronic device to a host, and the electronic device using the interface controller and a control method for the external electronic controller are disclosed. The interface controller has a control unit and a non-volatile memory. The control unit is configured to transmit a termination-on signal to the host when link information retrieved from the main body has been written into the non-volatile memory. When the host issues a link information request in response to the termination-on signal, the control unit uses the link information stored in the non-volatile memory to respond to the link information request.

Abstract translation: 公开了一种将外部电子设备的主体连接到主机的接口控制器，以及使用接口控制器的电子设备和外部电子控制器的控制方法。 接口控制器具有控制单元和非易失性存储器。 控制单元被配置为当从主体检索到的链接信息已被写入非易失性存储器时，向终端发送终止信号。 当主机响应于终止信号发出链接信息请求时，控制单元使用存储在非易失性存储器中的链接信息来响应链接信息请求。

公开(公告)号：US20150019925A1

公开(公告)日：2015-01-15

申请号：US14317108

申请日：2014-06-27

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Chin-Yin TSAI ,  Yi-Lin LAI

IPC: G11C29/08 ,  G11C29/56 ,  G06F12/02

CPC classification number: G11C29/08 ,  G06F12/0246 ,  G06F12/1416 ,  G06F2212/7211 ,  G11C16/00 ,  G11C16/349 ,  G11C29/12015 ,  G11C2029/0409 ,  G11C2029/4402

Abstract: An identification technique for physically damaged blocks of a flash memory of a data storage device. In the data storage device, a controller coupled to the flash memory writes data into the flash memory with at least one time stamp corresponding to the data. The time stamp is taken into consideration by the controller to identify the physically damaged blocks of the flash memory, and thereby it is prevented from erroneously identifying a physically undamaged block as bad. Thus, the flash memory is prevented from being erroneously regarded as a write protected memory. The lifespan of the flash memory is effectively prolonged.

Abstract translation: 一种用于数据存储设备的闪存的物理损坏块的识别技术。 在数据存储设备中，耦合到闪速存储器的控制器以对应于数据的至少一个时间戳将数据写入闪速存储器。 由控制器考虑时间标记以识别闪存的物理损坏块，从而防止错误地识别物理上没有损坏的块是不好的。 因此，防止闪存被错误地视为写保护存储器。 闪存的寿命有效延长。

公开(公告)号：US20150016191A1

公开(公告)日：2015-01-15

申请号：US14317138

申请日：2014-06-27

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Chin-Yin TSAI ,  Yi-Lin LAI

IPC: G11C16/32

CPC classification number: G11C16/32 ,  G11C29/023 ,  G11C29/028 ,  G11C29/12015

Abstract: An overclocking process for a data storage device using a flash memory. A controller for the flash memory tests the flash memory using test clocks with various frequencies to determine at least one clock signal suitable to the flash memory. The clock candidates suitable to the flash memory are selected from the test clocks. The flash memory is operated in a variable-frequency manner by which the flash memory is switched between the clock candidates, such that electromagnetic interference is spread over different bands.

Abstract translation: 使用闪存的数据存储设备的超频处理。 用于闪速存储器的控制器使用具有各种频率的测试时钟来测试闪存，以确定适合于闪存的至少一个时钟信号。 从测试时钟中选择适合闪存的时钟候选。 闪速存储器以可变频率的方式操作，通过该方式闪存在时钟候选之间切换，使得电磁干扰分布在不同的频带上。