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公开(公告)号：US11868644B1
公开(公告)日：2024-01-09
申请号：US17870616
申请日：2022-07-21
Applicant: VMware, Inc.
Inventor： Andreas Georg Nowatzyk , Isam Wadih Akkawi , Pratap Subrahmanyam , Adarsh Seethanadi Nayak , Nishchay Dua
CPC classification number: G06F3/0653 , G06F3/0611 , G06F3/0647 , G06F3/0683 , G06F12/0292 , G06F2212/1024
Abstract: In one set of embodiments, a hardware module of a computer system can receive a stream of addresses corresponding to memory units being accessed by a central processing unit (CPU) of the computer system. The hardware module can further generate a frequency estimate for each address in the stream of addresses, the frequency estimate being indicative of a number of times a memory unit identified by the address has been accessed by the CPU, and can determine, based on the generated frequency estimates, a set of n most frequently accessed memory units.
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公开(公告)号：US20240028243A1
公开(公告)日：2024-01-25
申请号：US17870616
申请日：2022-07-21
Applicant: VMware, Inc.
Inventor： Andreas Georg Nowatzyk , Isam Wadih Akkawi , Pratap Subrahmanyam , Adarsh Seethanadi Nayak , Nishchay Dua
CPC classification number: G06F3/0653 , G06F3/0611 , G06F3/0647 , G06F3/0683 , G06F12/0292 , G06F2212/1024
Abstract: In one set of embodiments, a hardware module of a computer system can receive a stream of addresses corresponding to memory units being accessed by a central processing unit (CPU) of the computer system. The hardware module can further generate a frequency estimate for each address in the stream of addresses, the frequency estimate being indicative of a number of times a memory unit identified by the address has been accessed by the CPU, and can determine, based on the generated frequency estimates, a set of n most frequently accessed memory units.
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公开(公告)号：US11880309B2
公开(公告)日：2024-01-23
申请号：US17355941
申请日：2021-06-23
Applicant: VMware, Inc.
Inventor： Nishchay Dua , Andreas Nowatzyk , Isam Wadih Akkawi , Pratap Subrahmanyam , Venkata Subhash Reddy Peddamallu , Adarsh Seethanadi Nayak
IPC: G06F12/0897 , G06F12/0831 , G06F12/0862
CPC classification number: G06F12/0897 , G06F12/0833 , G06F12/0862 , G06F2212/152
Abstract: The state of cache lines transferred into an out of caches of processing hardware is tracked by monitoring hardware. The method of tracking includes monitoring the processing hardware for cache coherence events on a coherence interconnect between the processing hardware and monitoring hardware, determining that the state of a cache line has changed, and updating a hierarchical data structure to indicate the change in the state of said cache line. The hierarchical data structure includes a first level data structure including first bits, and a second level data structure including second bits, each of the first bits associated with a group of second bits. The step of updating includes setting one of the first bits and one of the second bits in the group corresponding to the first bit that is being set, according to an address of said cache line.
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公开(公告)号：US11782832B2
公开(公告)日：2023-10-10
申请号：US17411792
申请日：2021-08-25
Applicant: VMware, Inc.
Inventor： Isam Wadih Akkawi , Andreas Nowatzyk , Pratap Subrahmanyam , Nishchay Dua , Adarsh Seethanadi Nayak , Venkata Subhash Reddy Peddamallu , Irina Calciu
IPC: G06F13/16 , G06F13/40 , G06F12/08 , G06F12/0804
CPC classification number: G06F12/0804 , G06F13/1668 , G06F13/4027 , G06F2212/1024 , G06F2212/1032
Abstract: In a computer system, a processor and an I/O device controller communicate with each other via a coherence interconnect and according to a cache coherence protocol. Registers of the I/O device controllers are mapped to the cache coherent memory space to allow the processor to treat the registers as cacheable memory. As a result, latency of processor commands executed by the I/O device controller is decreased, and size of data stored in the I/O device controller that can be accessed by the processor is increased from the size of a single register to the size of an entire cache line.
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