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    Multiple arbiter jitter estimation system and related techniques
    2.
    发明授权
    Multiple arbiter jitter estimation system and related techniques 失效
    多仲裁抖动估计系统及相关技术

    公开(公告)号：US06661860B1

    公开(公告)日：2003-12-09

    申请号：US09478106

    申请日：2000-01-04

    申请人： Vadim Gutnik ,  Anantha Chandrakasan

    发明人： Vadim Gutnik ,  Anantha Chandrakasan

    IPC分类号： H04L700

    CPC分类号： H04L1/205 ,  G01R29/26

    摘要： A digital circuit includes a plurality of arbiters, each arbiter having first and second input ports and an output port at which is provided an arbiter output signal. Each first input of the plurality of arbiters is connected to a first common line and each second input of the plurality of arbiters is connected to a second common line. The digital circuit further includes a decision circuit, having a plurality of inputs and an output, with each of the inputs of the decision circuit coupled to a corresponding one of the output of the plurality of arbiters. The decision circuit provides an output signal indicative of the time difference between a signal fed to the first common line and a signal fed to the second common line. With such an arrangement, phase jitter or timing jitter in a clock network can be measured with relatively high resolution and the system cam resolve cycle-by-cycle jitter with a predetermined resolution.

    摘要翻译： 数字电路包括多个仲裁器，每个仲裁器具有第一和第二输入端口以及输出端口，在该输出端口提供仲裁器输出信号。 多个仲裁器的每个第一输入连接到第一公共线，并且多个仲裁器的每个第二输入连接到第二公共线。 数字电路还包括具有多个输入和输出的判定电路，其中判决电路的每个输入耦合到多个仲裁器的输出中的对应的一个。 判定电路提供指示馈送到第一公共线的信号和馈送到第二公共线的信号之间的时间差的输出信号。 通过这样的布置，可以以相对高的分辨率测量时钟网络中的相位抖动或定时抖动，并且系统凸轮以预定分辨率解决逐周期抖动。

    RFID tags circuits and methods for sensing own power to predetermine feasibility of requested action
    6.
    发明授权
    RFID tags circuits and methods for sensing own power to predetermine feasibility of requested action 有权
    RFID标签电路和用于感测自身电力的方法，以预先确定所请求动作的可行性

    公开(公告)号：US07733227B1

    公开(公告)日：2010-06-08

    申请号：US11624197

    申请日：2007-01-17

    申请人： Alberto Pesavento ,  Vadim Gutnik ,  John D. Hyde

    发明人： Alberto Pesavento ,  Vadim Gutnik ,  John D. Hyde

    IPC分类号： G08B13/14

    CPC分类号： G06K7/0008 ,  G06K19/0707 ,  G06K19/0712 ,  G06K19/07749

    摘要： Feasibility of a requested action by a reader is predetermined in an RFID tag based on an available tag power level. A pretest that is designed to consume artificially high levels of power is performed and the power level monitored to determine if a preset condition is met. The pretest may include activation of selected components such as a memory and associated support circuitry. If the preset condition is not met, the requested action is aborted and an error message transmitted to the reader.

    摘要翻译： 基于可用的标签功率电平，RFID标签中预先确定读取器所请求的动作的可行性。 执行被设计为消耗人为高电平的预测试，并且监视功率电平以确定是否满足预设条件。 预测试可以包括激活所选择的组件，例如存储器和相关联的支持电路。 如果不满足预设条件，请求的操作将中止，并将错误消息传送给读卡器。

    RADIO-FREQUENCY IDENTIFICATION TAG WITH OSCILLATOR CALIBRATION
    7.
    发明申请
    RADIO-FREQUENCY IDENTIFICATION TAG WITH OSCILLATOR CALIBRATION 有权
    具有振荡器校准的无线电频率识别标签

    公开(公告)号：US20070001856A1

    公开(公告)日：2007-01-04

    申请号：US11460200

    申请日：2006-07-26

    申请人： Christopher Diorio ,  Vadim Gutnik ,  Todd Humes

    发明人： Christopher Diorio ,  Vadim Gutnik ,  Todd Humes

    IPC分类号： G08B13/14

    CPC分类号： G06K19/0723 ,  G06K19/0726

    摘要： A method of calibrating an oscillator within a Radio-Frequency Identification (RFID) tag includes storing a plurality of calibration values within a memory structure. Each of the calibration values corresponds to a respective oscillation frequency of the oscillator. A selected calibration value is selected from the plurality of calibration values stored, according to a first selection criterion. The oscillator is then calibrated in accordance with the selected calibration value.

    摘要翻译： 校准射频识别（RFID）标签内的振荡器的方法包括将多个校准值存储在存储器结构内。 每个校准值对应于振荡器的相应振荡频率。 根据第一选择标准，从存储的多个校准值中选择所选择的校准值。 然后根据所选择的校准值校准振荡器。

    Mixing, modulation and demodulation via electromechanical resonators
    8.
    发明授权
    Mixing, modulation and demodulation via electromechanical resonators 失效
    通过机电谐振器进行混频，调制和解调

    公开(公告)号：US5839062A

    公开(公告)日：1998-11-17

    申请号：US210199

    申请日：1994-03-18

    申请人： Clark Tu-Cuong Nguyen ,  Vadim Gutnik ,  Roger T. Howe

    发明人： Clark Tu-Cuong Nguyen ,  Vadim Gutnik ,  Roger T. Howe

    IPC分类号： H03H9/02 ,  H03H9/24 ,  H03H9/46 ,  H04B1/26

    CPC分类号： H03H9/2426 ,  H03H9/02377 ,  H03H9/465 ,  H04B1/26 ,  H03H2009/02496

    摘要： Mixing, modulation and demodulation using the nonlinear properties of microelectromechanical resonators and filters are described. Mixing followed by filtering is implemented using microelectromechanical filters with nonlinear input transducers. AM modulation is implemented by passing a carrier signal through the output transducer of a microelectromechanical filter. FM and FSK demodulation is accomplished using parallel banks of microelectromechanical filters. The invention can be implemented using integrated circuit technology.

    摘要翻译： 描述使用微机电谐振器和滤波器的非线性特性的混频，调制和解调。 使用具有非线性输入传感器的微机电滤波器实现混频，随后进行滤波。 通过使载波信号通过微机电滤波器的输出换能器来实现AM调制。 FM和FSK解调是使用微机电滤波器的并行库实现的。 本发明可以使用集成电路技术实现。

    Redundant non-volatile memory cell
    9.
    发明授权
    Redundant non-volatile memory cell 有权
    冗余的非易失性存储单元

    公开(公告)号：US07679957B2

    公开(公告)日：2010-03-16

    申请号：US11106982

    申请日：2005-04-15

    申请人： Yanjun Ma ,  William T. Colleran ,  Vadim Gutnik

    发明人： Yanjun Ma ,  William T. Colleran ,  Vadim Gutnik

    IPC分类号： G11C16/06

    CPC分类号： G11C29/789 ,  G11C29/76

    摘要： Two floating gate devices are arranged in a redundant configuration in a non-volatile memory (NVM) such that stress induced leakage current (SILC) or other failures do not result in a complete loss of memory storage. The redundant NVM may be arranged as a series configuration, a parallel configuration, a single-ended device, a differential device, a simple logic circuit function, a complex logic circuit function, and/or as part of an RFID tag system.

    摘要翻译： 两个浮置栅极器件以非易失性存储器（NVM）中的冗余配置布置，使得应力诱发的漏电流（SILC）或其他故障不会导致存储器存储的完全丢失。 冗余NVM可以被布置为串联配置，并行配置，单端设备，差分设备，简单逻辑电路功能，复杂逻辑电路功能和/或作为RFID标签系统的一部分。

    Slice voltage compensation
    10.
    发明授权
    Slice voltage compensation 有权
    切片电压补偿

    公开(公告)号：US07453388B1

    公开(公告)日：2008-11-18

    申请号：US10303398

    申请日：2002-11-25

    申请人： Vadim Gutnik ,  Jerrell P. Hein

    发明人： Vadim Gutnik ,  Jerrell P. Hein

    IPC分类号： H03M1/12

    CPC分类号： H04B10/695 ,  H03M3/354 ,  H03M3/43 ,  H03M3/456

    摘要： An integrated circuit includes an internal resistance (RINT) and a compensation circuit coupled to adjust a slice level specified by a slice signal to a compensated slice level according to a difference between the internal resistance (RINT) and a known resistance (REXT). A reference voltage is coupled to the internal resistance to generate an internal current and is coupled to the known resistance to generate a known current. The compensated slice level is determined according to the internal current and the known current. The compensated slice level may be generated using an analog to digital converter coupled to a digital to analog converter that scale original slice signal based on the internal and known currents.

    摘要翻译： 集成电路包括内部电阻（R INT1）和补偿电路，该补偿电路被耦合以根据内部电阻（R INT ）和已知电阻（R EXT ）。 参考电压耦合到内部电阻以产生内部电流并且耦合到已知电阻以产生已知电流。 补偿限幅电平根据内部电流和已知电流来确定。 可以使用耦合到数模转换器的模数转换器来生成补偿限幅电平，该转换器基于内部和已知电流来缩放原始限幅信号。