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公开(公告)号：US07454647B1
公开(公告)日：2008-11-18
申请号：US11192426
申请日：2005-07-28
CPC分类号： G01R31/31726 , G01R31/31937
摘要： A skew measurement system and method wherein each of the signals among which the skew is to be determined is connected one at a time to a clock recovery loop. The locked state of the clock recovery loop is used as an indicator of the skew of the data signal relative to the internal clock of the clock recovery loop. By measuring the difference between the locked state of different signals, their relative skew can be measured.
摘要翻译： 歪斜测量系统和方法，其中要确定歪斜的每个信号一次一个地连接到时钟恢复环路。 时钟恢复环路的锁定状态用作数据信号相对于时钟恢复环路内部时钟的偏斜的指示。 通过测量不同信号的锁定状态之间的差异，可以测量它们的相对偏差。
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2.发明授权公开(公告)号：US07307458B1
公开(公告)日：2007-12-11
申请号：US11139918
申请日：2005-05-27
CPC分类号： H04L25/028 , G06F13/4072 , H04L25/0278
摘要： A serial communication interface driver is provided wherein current steering switches are also used to provide termination impedances. The output voltage can be produced by a voltage-dividing current path between two regulated voltages, which provides improved efficiency.
摘要翻译： 提供了串行通信接口驱动器，其中当前的转向开关也用于提供端接阻抗。 输出电压可以通过两个调节电压之间的分压电流路径产生，这提高了效率。
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公开(公告)号：US07208981B1
公开(公告)日：2007-04-24
申请号：US10907904
申请日：2005-04-20
IPC分类号： H03K5/22
CPC分类号： H04L25/028 , H04L1/24 , H04L25/0272
摘要： A circuit and method are provided for performing built-in test of output signal magnitudes of integrated differential signal generator circuitry. In accordance with one embodiment, first upper and lower reference voltages and second upper and lower reference voltages are received via a plurality of reference electrodes, wherein: a difference between the first and upper and lower reference voltages comprises a first difference magnitude; a difference between the second upper and lower reference voltages comprises a second difference magnitude; and the first difference magnitude is greater than the second difference magnitude. Test signal generator circuitry provides a plurality of binary signals with respective successions of opposing signal states. Differential signal generator circuitry, coupled to the test signal generator circuitry and responsive to the plurality of binary signals, provides a plurality of differential signals having respective magnitudes related to the respective successions of opposing binary signal states. Signal comparison circuitry, coupled to the plurality of reference electrodes and the differential signal generator circuitry, and responsive to the first and second upper and lower reference signals and the plurality of differential signals, provides a plurality of test signals with respective test signal states indicative of whether respective ones of the differential signal magnitudes are within a range defined as being less than the first difference magnitude and greater than the second difference magnitude.
摘要翻译： 提供了一种电路和方法，用于对集成差分信号发生器电路的输出信号幅值进行内置测试。 根据一个实施例，经由多个参考电极接收第一上参考电压和第二上参考电压和第二上基准电压和下参考电压，其中：第一和上参考电压之间的差包括第一差幅度; 第二上参考电压和下参考电压之间的差包括第二差值; 并且第一差值幅度大于第二差值幅度。 测试信号发生器电路提供具有各自相对的信号状态的多个二进制信号。 耦合到测试信号发生器电路并响应于多个二进制信号的差分信号发生器电路提供具有与相应二进制信号状态的相应序列相关的相应幅度的多个差分信号。 耦合到多个参考电极和差分信号发生器电路并且响应于第一和第二上参考信号和下参考信号和多个差分信号的信号比较电路提供多个测试信号，其中各测试信号状态指示 差分信号幅度中的各个是否在限定为小于第一差分幅度并大于第二差值的范围内。
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公开(公告)号：US08294473B2
公开(公告)日：2012-10-23
申请号：US12423704
申请日：2009-04-14
申请人： Robert Karl Butler , Vijaya Ceekala , Jim Wieser
发明人： Robert Karl Butler , Vijaya Ceekala , Jim Wieser
IPC分类号： G01R31/02
CPC分类号： G01R19/16528
摘要： A cable detector includes one or more peak detectors that detect when a termination impedance is missing from the output of a line driver. A peak detection signal is asserted when signals on a transmission line exceed a threshold level. A fault condition is asserted when the peak detection signal is asserted for a sufficient length of time to indicate that an actual fault is detected. The time period required for detecting a lost or missing line termination is longer than the time periods for any one of the pathological conditions to avoid a false positive detection. After the peak detection signal is de-asserted, the fault condition will be maintained until another sufficient length of time has expired without a peak detection.
摘要翻译： 电缆检测器包括一个或多个峰值检测器，其检测何时从线路驱动器的输出丢失终端阻抗。 当传输线上的信号超过阈值电平时，峰值检测信号被断言。 当峰值检测信号被断言足够的时间长度以指示检测到实际故障时，断言故障条件。 检测丢失或缺失线终止所需的时间长于任何一种病理状况的时间段，以避免假阳性检测。 在峰值检测信号被取消断言之后，故障状态将保持到另一个足够长的时间到期而没有峰值检测。
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5.发明授权Apparatus and method for automatic gain control and echo cancellation in a network system 有权网络系统中自动增益控制和回波消除的装置和方法公开(公告)号：US07813495B1
公开(公告)日：2010-10-12
申请号：US11183245
申请日：2005-07-16
申请人： Ramsin M. Ziazadeh , Vijaya Ceekala
发明人： Ramsin M. Ziazadeh , Vijaya Ceekala
CPC分类号： H04B3/235 , H04L25/0272
摘要： A communications cabling front-end architecture that achieves solid echo cancellation and lower noise performance by combining an echo-cancellation circuit and an equalizer function at the same point, at the most front-end of the system.
摘要翻译： 通信电缆前端架构，通过在系统最前端的同一点组合回波消除电路和均衡器功能，实现固体回波消除和降低噪声性能。
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6.发明授权公开(公告)号：US07649409B1
公开(公告)日：2010-01-19
申请号：US11877255
申请日：2007-10-23
申请人： Yongseon Koh , Babak Matinpour , Vijaya Ceekala , Ramsin Ziazadeh
发明人： Yongseon Koh , Babak Matinpour , Vijaya Ceekala , Ramsin Ziazadeh
IPC分类号： H03B1/00
CPC分类号： H04B3/14 , H03F3/45085 , H03F3/45475
摘要： An integrated circuit comprises a pin coupled to receive signals from outside the integrated circuit and an input network. The input network equalizes incoming signals by attenuating lower frequency input signals more than higher frequency input signals received at the pin. The input network is configured to generate a DC bias voltage at an output of the input network in response to an AC coupled input signal or a DC coupled input signal received at the pin with a wide common-mode range.
摘要翻译： 集成电路包括被耦合以从集成电路外部接收信号的引脚和输入网络。 输入网络通过衰减低频输入信号来均衡输入信号，而不是在引脚处接收的高频输入信号。 输入网络被配置为响应于AC耦合输入信号或在具有宽共模范围的引脚处接收的DC耦合输入信号，在输入网络的输出处产生DC偏置电压。
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7.发明授权Built-in test circuit for testing AC transfer characteristic of high-speed analog circuit 有权内置测试电路，用于测试高速模拟电路的交流传输特性公开(公告)号：US07994807B1
公开(公告)日：2011-08-09
申请号：US11877519
申请日：2007-10-23
申请人： Yongseon Koh , Babak Matinpour , Vijaya Ceekala
发明人： Yongseon Koh , Babak Matinpour , Vijaya Ceekala
IPC分类号： G01R31/3187
CPC分类号： G01R31/2884
摘要： An analog device under test circuit and a built-in test circuit for testing an AC transfer characteristic of the analog device under test are fabricated on an integrated circuit. The built-in test circuit includes an amplitude detector that detects the amplitude of the output signal of the analog device under test. The test time is reduced by sampling in real-time the DC value corresponding to the amplitude of the analog device under test. An additional reduction in the test time is achieved by using comparators with upper and lower limit reference signals and a pass-fail logic test.
摘要翻译： 一个模拟器件被测电路和一个用于测试被测模拟器件的交流传输特性的内置测试电路是在集成电路上制造的。 内置测试电路包括检测被测模拟器件的输出信号振幅的振幅检测器。 通过实时采样对应于被测模拟装置的幅度的DC值，可以减少测试时间。 通过使用具有上限和下限参考信号的比较器和通过失效逻辑测试来实现测试时间的进一步减少。
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8.发明授权公开(公告)号：US06262603B1
公开(公告)日：2001-07-17
申请号：US09515183
申请日：2000-02-29
IPC分类号： H03K522
CPC分类号： H03H7/0153 , H03B5/20 , H03H2210/043
摘要： An RC calibration circuit, which utilizes a resistor and a variable capacitor connected in parallel, reduces power consumption and increases the accuracy of the calibration by comparing the voltage on the resistor to the voltage on the capacitor after a predetermined time has expired since the capacitor began charging up. The result of the comparison, which indicates whether the voltage on the resistor is greater than the voltage on the capacitor, is then used to adjust the capacitance of the capacitor to servo the RC time constant to a predetermined value.
摘要翻译： 使用电阻器和可变电容并联连接的RC校准电路通过将电阻器上的电压与电容器上的电压进行比较，降低功耗并提高校准精度，这是由于电容器开始 充电 比较结果表明，电阻器上的电压是否大于电容器上的电压，然后用于调整电容器的电容以使RC时间常数维持在预定值。
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公开(公告)号：US20090309611A1
公开(公告)日：2009-12-17
申请号：US12423704
申请日：2009-04-14
申请人： Robert Karl Butler , Vijaya Ceekala , Jim Wieser
发明人： Robert Karl Butler , Vijaya Ceekala , Jim Wieser
IPC分类号： G01R31/00
CPC分类号： G01R19/16528
摘要： A cable detector includes one or more peak detectors that detect when a termination impedance is missing from the output of a line driver. A peak detection signal is asserted when signals on a transmission line exceed a threshold level. A fault condition is asserted when the peak detection signal is asserted for a sufficient length of time to indicate that an actual fault is detected. The time period required for detecting a lost or missing line termination is longer than the time periods for any one of the pathological conditions to avoid a false positive detection. After the peak detection signal is de-asserted, the fault condition will be maintained until another sufficient length of time has expired without a peak detection.
摘要翻译： 电缆检测器包括一个或多个峰值检测器，其检测何时从线路驱动器的输出丢失终端阻抗。 当传输线上的信号超过阈值电平时，峰值检测信号被断言。 当峰值检测信号被断言足够的时间长度以指示检测到实际故障时，断言故障条件。 检测丢失或缺失线终止所需的时间长于任何一种病理状况的时间段，以避免假阳性检测。 在峰值检测信号被取消断言之后，故障状态将保持到另一个足够长的时间到期而没有峰值检测。
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10.发明授权公开(公告)号：US06177789B1
公开(公告)日：2001-01-23
申请号：US09495133
申请日：2000-01-31
IPC分类号： G05F316
CPC分类号： H04L25/028
摘要： A line driver outputs a pair of transmit signals TX+ and TX− that have substantially reduced output level variations due to variations in process, voltage, and temperature. The reduced output level variations are provided by varying the magnitude of the current that sets up the voltages of the transmit signals in a manner that offsets variations in the power supply voltage, temperature, and process, and by limiting variations of the bandgap current source to process and temperature only.
摘要翻译： 线路驱动器输出一对发射信号TX +和TX-，其由于过程，电压和温度的变化而具有显着降低的输出电平变化。 减小的输出电平变化通过改变设置发射信号的电压的电流的大小来提供，该电流以抵消电源电压，温度和过程的变化的方式，并且通过将带隙电流源的变化限制为 过程和温度。
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