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    Ion implant for defect control
    4.
    发明授权
    Ion implant for defect control 有权
    离子注入用于缺陷控制

    公开(公告)号：US09299564B2

    公开(公告)日：2016-03-29

    申请号：US13897666

    申请日：2013-05-20

    申请人： Varian Semiconductor Equipment Associates, Inc.

    发明人： Andrew M. Waite ,  Stanislav S. Todorov

    IPC分类号： H01L21/322 ,  H01L21/223 ,  H01L29/66 ,  H01L21/265

    CPC分类号： H01L21/2236 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/66803

    摘要： Various methods for implanting dopant ions into a three dimensional feature of a semiconductor wafer are disclosed. The implant temperature may be varied to insure that the three dimensional feature, after implant, has a crystalline inner core, which is surrounded by an amorphized surface layer. The crystalline core provides a template from which the crystalline structure for the rest of the feature can be regrown. In some embodiments, the implant energy and the implant temperature may each be modified to achieve the desired crystalline inner core with the surrounding amorphized surface layer.

    摘要翻译： 公开了将掺杂剂离子注入到半导体晶片的三维特征中的各种方法。 植入物温度可以变化以确保植入后的三维特征具有被非晶化表面层包围的结晶内核。 晶核提供了一种模板，其中可以再生长其它特征的晶体结构。 在一些实施例中，植入能量和植入物温度可各自被修改以实现具有周围非晶化表面层的期望的晶体内核。

    Method Of Doping A Polycrystalline Transistor Channel For Vertical NAND Devices
    6.
    发明申请
    Method Of Doping A Polycrystalline Transistor Channel For Vertical NAND Devices 有权
    掺杂用于垂直NAND器件的多晶硅晶体管通道的方法

    公开(公告)号：US20150017772A1

    公开(公告)日：2015-01-15

    申请号：US13938713

    申请日：2013-07-10

    申请人： Varian Semiconductor Equipment Associates, Inc.

    发明人： Andrew M. Waite ,  Jonathan Gerald England ,  Rajesh Prasad

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11582 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/26586 ,  H01L29/66833 ,  H01L29/7926

    摘要： A method of doping the polycrystalline channel in a vertical FLASH device is disclosed. This method uses a plurality of high energy ion implants to dope the channel at various depths of the channel. In some embodiments, these ion implants are performed at an angle offset from the normal direction, such that the implanted ions pass through at least a portion of the surrounding ONO stack. By passing through the ONO stack, the distribution of ranges reached by each ion may differ from that created by a vertical implant.

    摘要翻译： 公开了一种在垂直FLASH装置中掺杂多晶硅通道的方法。 该方法使用多个高能离子植入物在通道的各种深度处掺杂通道。 在一些实施例中，这些离子植入物以与法线方向偏移的角度执行，使得注入的离子穿过周围的ONO堆叠的至少一部分。 通过ONO堆叠，每个离子达到的范围分布可能与垂直植入物所产生的范围不同。

    Techniques and structure for forming thin silicon-on-insulator materials
    7.
    发明授权
    Techniques and structure for forming thin silicon-on-insulator materials 有权

    公开(公告)号：US10600675B2

    公开(公告)日：2020-03-24

    申请号：US15728000

    申请日：2017-10-09

    申请人： Varian Semiconductor Equipment Associates, Inc.

    发明人： Andrew M. Waite ,  Morgan D. Evans ,  John Hautala

    IPC分类号： H01L21/762 ,  H01L21/311 ,  H01L21/02 ,  H01L27/12 ,  H01J37/305 ,  H01L21/3065

    摘要： A method may include providing a silicon-on-insulator (SOI) substrate, the SOI substrate comprising an insulator layer and a silicon layer. The silicon layer may be disposed on the insulator layer, where the silicon layer comprises a first silicon thickness variation. The method may include forming an oxide layer on the silicon layer, where the oxide layer has a uniform thickness. The method may include selectively etching the oxide layer on the silicon layer, wherein the oxide layer comprises a first non-uniform oxide thickness. After thermal processing of the SOI substrate in an oxygen ambient, the non-uniform oxide thickness may be configured to generate a second silicon thickness variation in the silicon layer, less than the first silicon thickness variation.

    Techniques and Structure for Forming Thin Silicon-on-Insulator Materials
    8.
    发明申请
    Techniques and Structure for Forming Thin Silicon-on-Insulator Materials 审中-公开

    公开(公告)号：US20190027396A1

    公开(公告)日：2019-01-24

    申请号：US15728000

    申请日：2017-10-09

    申请人： Varian Semiconductor Equipment Associates, Inc.

    发明人： Andrew M. Waite ,  Morgan D. Evans ,  John Hautala

    IPC分类号： H01L21/762 ,  H01L27/12 ,  H01L21/02 ,  H01L21/311

    摘要： A method may include providing a silicon-on-insulator (SOI) substrate, the SOI substrate comprising an insulator layer and a silicon layer. The silicon layer may be disposed on the insulator layer, where the silicon layer comprises a first silicon thickness variation. The method may include forming an oxide layer on the silicon layer, where the oxide layer has a uniform thickness. The method may include selectively etching the oxide layer on the silicon layer, wherein the oxide layer comprises a first non-uniform oxide thickness. After thermal processing of the SOI substrate in an oxygen ambient, the non-uniform oxide thickness may be configured to generate a second silicon thickness variation in the silicon layer, less than the first silicon thickness variation.

    Masking For High Temperature Implants
    10.
    发明申请
    Masking For High Temperature Implants 有权
    高温植入物掩蔽

    公开(公告)号：US20170025277A1

    公开(公告)日：2017-01-26

    申请号：US14807377

    申请日：2015-07-23

    申请人： Varian Semiconductor Equipment Associates, Inc.

    发明人： Andrew M. Waite ,  Naushad Variam

    IPC分类号： H01L21/266 ,  H01L21/308 ,  H01L21/311 ,  H01L21/02

    CPC分类号： H01L21/266 ,  H01L21/02115 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/3081 ,  H01L21/31116

    摘要： A method for the selective implantation of a workpiece is disclosed. In place of conventional photoresist, a two layer structure is used. The first layer, referred to as the protective layer, is applied directly to the workpiece and protects the workpiece from harmful etching processes. Additionally, the protective layer has limited ability to stop ions from impacting the workpiece. The second layer, referred to as the blocking layer, which is formed on a portion of the protective layer, is used to block ions from impacting the underlying workpiece. Advantageously, the blocking layer may be selectively etched without affecting the protective layer. Additionally, the protective layer can be removed without affecting the underlying workpiece. Through the use of this two layer technique, high temperature selective implants may be performed on a variety of different semiconductor devices.

    摘要翻译： 公开了一种选择性植入工件的方法。 代替常规光致​​抗蚀剂，使用两层结构。 称为保护层的第一层直接施加到工件上，并保护工件免受有害的蚀刻工艺。 此外，保护层具有限制离子撞击工件的能力有限。 被称为阻挡层的第二层，形成在保护层的一部分上，用于阻止离子冲击下面的工件。 有利地，阻挡层可以被选择性地蚀刻而不影响保护层。 此外，可以去除保护层而不影响下面的工件。 通过使用这种两层技术，可以对各种不同的半导体器件执行高温选择性植入。