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    Method of applying stresses to PFET and NFET transistor channels for improved performance
    2.
    发明申请
    Method of applying stresses to PFET and NFET transistor channels for improved performance 有权
    向PFET和NFET晶体管通道施加应力以提高性能的方法

    公开(公告)号：US20070122982A1

    公开(公告)日：2007-05-31

    申请号：US11657154

    申请日：2007-01-24

    申请人： Victor Chan ,  Yong Lee ,  Haining Yang

    发明人： Victor Chan ,  Yong Lee ,  Haining Yang

    IPC分类号： H01L21/8234

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L29/665

    摘要： A method is provided for fabricating a semiconductor device structure. In such method a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), each of the NFET and the PFET having a conduction channel disposed in a single-crystal semiconductor region of a substrate. A stressed film having a compressive stress at a first magnitude can be formed to overlie the PFET and the NFET. Desirably, a mask is formed to cover the PFET while exposing the NFET, after which, desirably, a portion of the stressed film overlying the NFET is subjected to ion implantation, while the mask protects another portion of the stressed film overlying the PFET from the ion implantation. The substrate can then be annealed, whereby, desirably, the compressive stress of the implanted portion of the stressed film is much reduced from the first magnitude by the annealing. In such way, the implanted portion of the stressed film overlying the NFET desirably imparts one of a much reduced magnitude compressive stress, a zero stress and a tensile stress to the conduction channel of the NFET. Another portion of the stressed film can continue to impart the compressive stress at the first magnitude to the conduction channel of the PFET.

    摘要翻译： 提供了制造半导体器件结构的方法。 在这种方法中，p型场效应晶体管（PFET）和n型场效应晶体管（NFET），NFET和PFET中的每一个具有设置在基板的单晶半导体区域中的导电沟道。 可以形成具有第一大小的压应力的应力膜覆盖在PFET和NFET上。 期望地，形成掩模以在暴露NFET的同时覆盖PFET，之后理想地，覆盖NFET的应力膜的一部分经受离子注入，而掩模保护覆盖PFET的应力膜的另一部分与 离子注入。 然后可以对衬底进行退火，因此期望地，应力膜的注入部分的压缩应力通过退火从第一量级大大降低。 以这种方式，覆盖NFET的应力膜的注入部分期望地将大大减小的压缩应力，零应力和拉伸应力中的一个施加到NFET的传导通道。 应力膜的另一部分可以继续将第一大小的压应力赋予PFET的传导通道。

    Method to enhance device performance with selective stress relief
    3.
    发明申请
    Method to enhance device performance with selective stress relief 有权
    通过选择性应力消除来增强设备性能的方法

    公开(公告)号：US20070134870A1

    公开(公告)日：2007-06-14

    申请号：US11299542

    申请日：2005-12-12

    申请人： Yong Lee ,  Haining Yang ,  Victor Chan

    发明人： Yong Lee ,  Haining Yang ,  Victor Chan

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

    摘要： A structure and method of fabrication of a semiconductor device having a stress relief layer under a stress layer in one region of a substrate. In a first example, a stress relief layer is formed over a first region of the substrate (e.g., PFET region) and not over a second region (e.g., NFET region). A stress layer is over the stress relief layer in the first region and over the devices and substrate/silicide in the second region. The NFET transistor performance is enhanced due to the overall tensile stress in the NFET channel while the degradation in the PFET transistor performance is reduced/eliminated due to the inclusion of the stress relief layer. In a second example embodiment, the stress relief layer is formed over the second region, but not the first region and the stress of the stress layer is reversed.

    摘要翻译： 在衬底的一个区域中的应力层下方具有应力消除层的半导体器件的制造结构和方法。 在第一示例中，应力消除层形成在衬底的第一区域（例如，PFET区域）上，而不是在第二区域（例如，NFET区域）之上。 应力层在第一区域中的应力消除层上方和第二区域中的器件和衬底/硅化物之上。 NFET晶体管的性能由于NFET沟道中的整体拉伸应力而增强，而由于包含应力消除层而降低/消除了PFET晶体管性能的降低。 在第二示例性实施例中，应力消除层形成在第二区域上，但不是第一区域并且应力层的应力被反转。

    STRUCTURE AND METHOD OF APPLYING STRESSES TO PFET AND NFET TRANSISTOR CHANNELS FOR IMPROVED PERFORMANCE
    4.
    发明申请
    STRUCTURE AND METHOD OF APPLYING STRESSES TO PFET AND NFET TRANSISTOR CHANNELS FOR IMPROVED PERFORMANCE 有权
    将应力施加到用于改进性能的PFET和NFET晶体管通道的结构和方法

    公开(公告)号：US20060113568A1

    公开(公告)日：2006-06-01

    申请号：US10904808

    申请日：2004-11-30

    申请人： Victor Chan ,  Yong Lee ,  Haining Yang

    发明人： Victor Chan ,  Yong Lee ,  Haining Yang

    IPC分类号： H01L27/10

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L29/665

    摘要： A semiconductor device structure is provided which includes a first semiconductor device; a second semiconductor device; and a unitary stressed film disposed over both the first and second semiconductor devices. The stressed film has a first portion overlying the first semiconductor device, the first portion imparting a first magnitude compressive stress to a conduction channel of the first semiconductor device, the stressed film further having a second portion overlying the second semiconductor device, the second portion not imparting the first magnitude compressive stress to a conduction channel of the second semiconductor device, the second portion including an ion concentration not present in the second portion such that the second portion imparts one of a compressive stress having a magnitude much lower than the first magnitude, zero stress, and a tensile stress to the conduction channel of the second semiconductor device.

    摘要翻译： 提供一种半导体器件结构，其包括第一半导体器件; 第二半导体器件; 以及设置在第一和第二半导体器件两者上的单一应力膜。 应力膜具有覆盖第一半导体器件的第一部分，第一部分向第一半导体器件的导电通道施加第一大小压缩应力，应力膜还具有覆盖第二半导体器件的第二部分，第二部分不 将第一强度压缩应力施加到第二半导体器件的导电通道，第二部分包括不存在于第二部分中的离子浓度，使得第二部分施加具有远低于第一大小的量级的压缩应力之一， 零应力和对第二半导体器件的导电通道的拉伸应力。

    Increasing carrier mobility in NFET and PFET transistors on a common wafer
    5.
    发明授权
    Increasing carrier mobility in NFET and PFET transistors on a common wafer 有权
    在普通晶圆上增加NFET和PFET晶体管的载流子迁移率

    公开(公告)号：US07211869B2

    公开(公告)日：2007-05-01

    申请号：US11110767

    申请日：2005-04-21

    申请人： Victor Chan ,  Haining Yang

    发明人： Victor Chan ,  Haining Yang

    IPC分类号： H01L31/00

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/092

    摘要： Enhanced carrier mobility in transistors of differing (e.g. complementary) conductivity types is achieved on a common chip by provision of two or more respective stressed layers, such as etch stop layers, overlying the transistors with stress being wholly or partially relieved in portions of the respective layers, preferably by implantations with heavy ions such as germanium, arsenic, xenon, indium, antimony, silicon, nitrogen oxygen or carbon in accordance with a block-out mask. The distribution and small size of individual areas of such stressed structures also prevents warping or curling of even very thin substrates.

    摘要翻译： 通过提供两个或更多个相应的应力层（例如覆盖晶体管的相应的应力层，例如蚀刻停止层），在共同的芯片上实现增强的不同（例如互补）导电类型的晶体管中的载流子迁移率，其中应力在相应的部分中被部分地完全或部分缓解 层，优选通过根据阻挡掩模的重离子如锗，砷，氙，铟，锑，硅，氮氧或碳的注入。 这种应力结构的各个区域的分布和小尺寸也防止甚至非常薄的基底的翘曲或卷曲。

    Increasing carrier mobility in NFET and PFET transistors on a common wafer
    8.
    发明授权
    Increasing carrier mobility in NFET and PFET transistors on a common wafer 有权
    在普通晶圆上增加NFET和PFET晶体管的载流子迁移率

    公开(公告)号：US06939814B2

    公开(公告)日：2005-09-06

    申请号：US10695754

    申请日：2003-10-30

    申请人： Victor Chan ,  Haining Yang

    发明人： Victor Chan ,  Haining Yang

    IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L21/31

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/092

    摘要： Enhanced carrier mobility in transistors of differing (e.g. complementary) conductivity types is achieved on a common chip by provision of two or more respective stressed layers, such as etch stop layers, overlying the transistors with stress being wholly or partially relieved in portions of the respective layers, preferably by implantations with heavy ions such as germanium, arsenic, xenon, indium, antimony, silicon, nitrogen oxygen or carbon in accordance with a block-out mask. The distribution and small size of individual areas of such stressed structures also prevents warping or curling of even very thin substrates.

    摘要翻译： 通过提供两个或更多个相应的应力层（例如覆盖晶体管的相应的应力层，例如蚀刻停止层），在共同的芯片上实现增强的不同（例如互补）导电类型的晶体管中的载流子迁移率，其中应力在相应的部分中被部分地完全或部分缓解 层，优选通过根据阻挡掩模的重离子如锗，砷，氙，铟，锑，硅，氮氧或碳的注入。 这种应力结构的各个区域的分布和小尺寸也防止甚至非常薄的基底的翘曲或卷曲。

    Double anneal with improved reliability for dual contact etch stop liner scheme
    9.
    发明申请
    Double anneal with improved reliability for dual contact etch stop liner scheme 有权
    双重退火，具有改进的双接触蚀刻停止衬垫方案的可靠性

    公开(公告)号：US20070138564A1

    公开(公告)日：2007-06-21

    申请号：US11304455

    申请日：2005-12-15

    申请人： Khee Lim ,  Victor Chan ,  Eng Lim ,  Wenhe Lin ,  Jamin Fen

    发明人： Khee Lim ,  Victor Chan ,  Eng Lim ,  Wenhe Lin ,  Jamin Fen

    IPC分类号： H01L21/8238 ,  H01L29/78

    CPC分类号： H01L21/823807 ,  H01L21/3003 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/823864 ,  H01L29/7843

    摘要： A method for forming a device with both PFET and NFET transistors using a PFET compressive etch stop liner and a NFET tensile etch stop liner and two anneals in a deuterium containing atmosphere. The method comprises: providing a NFET transistor in a NFET region and a PFET transistor in a PFET region. We form a NFET tensile contact etch-stop liner over the NFET region. Then we perform a first deuterium anneal. We form a PFET compressive etch stop liner over the PFET region. We form a (ILD) dielectric layer with contact openings over the substrate. We perform a second deuterium anneal. The temperature of the second deuterium anneal is less than the temperature of the first deuterium anneal.

    摘要翻译： 使用PFET压缩蚀刻停止衬垫和NFET拉伸蚀刻停止衬垫以及在含氘气氛中的两个退火来形成具有PFET和NFET晶体管的器件的方法。 该方法包括：在PFET区域中的NFET区域中提供NFET晶体管和PFET晶体管。 我们在NFET区域上形成NFET拉伸接触蚀刻停止衬垫。 然后我们进行第一次氘退火。 我们在PFET区域上形成PFET压电蚀刻停止衬垫。 我们在衬底上形成具有接触开口的（ILD）电介质层。 我们进行第二次氘退火。 第二次氘退火的温度小于第一次氘退火的温度。