-
1.发明授权
公开(公告)号：US5724249A
公开(公告)日：1998-03-03
申请号：US461961
申请日：1995-06-05
IPC分类号： H03K19/20 , H03K19/00 , H03K19/096 , H03K19/02 , H03K19/094
CPC分类号： H03K19/0016
摘要： A "no select state" is implemented with self-resetting CMOS logic circuitry so as to essentially disable the resetting function of this logic circuitry when the logic circuitry is in an idle state. As an example, within a multiplier circuit in a processor, the selection inputs to a multiplexor circuit are de-selected when there is no need for the multiplier circuitry.
摘要翻译： 利用自复位CMOS逻辑电路实现“无选择状态”，以便当逻辑电路处于空闲状态时基本上禁用该逻辑电路的复位功能。 例如，在处理器的乘法器电路中，当不需要乘法器电路时，对多路复用器电路的选择输入被取消选择。
-
公开(公告)号：US06389577B1
公开(公告)日：2002-05-14
申请号：US09276389
申请日：1999-03-25
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A method and implementing system is provided in which input signal specifications, element internal delays and output loads, for each element in a circuit design, are utilized in an iterative processing engine to objectively determine and provide a timing rule database for a circuit being designed. A schematic database netlist is run through a test model converter program to provide a test model database at a gate level for the test model design circuit. These data are processed by a designer through a workstation GUI and the result is applied to an I/O design testing function. The results of the I/O design testing function include a listing of patterns of input combinations which are needed to get listed outputs. The GUI prepares a sequence of stimuli to test the circuit with a timing simulator. Based on the output response of the timing simulator, delay relationships under various input and output load conditions are compiled.
摘要翻译： 提供了一种方法和实现系统，其中针对电路设计中的每个元件的输入信号规范，元件内部延迟和输出负载在迭代处理引擎中被利用以客观地确定并为所设计的电路提供定时规则数据库。 示意图数据库网表通过测试模型转换器程序运行，以在测试模型设计电路的门级提供测试模型数据库。 这些数据由设计人员通过工作站GUI进行处理，结果应用于I / O设计测试功能。 I / O设计测试功能的结果包括列出输出组合的列表，这些输入组合是列出输出所需的。 GUI准备一系列刺激，以使用定时模拟器测试电路。 基于定时仿真器的输出响应，编译了各种输入和输出负载条件下的延迟关系。
-
公开(公告)号：US5771186A
公开(公告)日：1998-06-23
申请号：US483768
申请日：1995-06-07
CPC分类号： G06F7/5324 , G06F7/5338
摘要： A multiplier circuit within a CPU has its selections of partial products reordered in a unique manner so that shift left capabilities are eliminated and the hardware is required to only perform shift right operations. This allows for reduced circuit sizes in several components within the multiplier circuit in order to save area, speed computation time, and reduce power consumption on the chip.
摘要翻译： CPU内的乘法器电路具有以独特方式重新排序的部分产品的选择，从而消除了左移功能，并且硬件仅需执行换档操作。 这允许在乘法器电路内的几个组件中减小电路尺寸，以便节省面积，速度计算时间，并降低芯片上的功耗。
-
公开(公告)号：US06002271A
公开(公告)日：1999-12-14
申请号：US854368
申请日：1997-05-12
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： Circuitry for eliminating charge sharing noise in MOS dynamic logic circuits is described. Dynamic logic circuits having stacks of MOS devices controlling the state of a common node defining the output logic state of the circuit are susceptible to charge sharing noise. This noise ultimately arises from leakage and stray capacitances at the nodes between MOS devices in each stack which the common node must supply. The noise is eliminated by employing MOS devices associated with the MOS devices in the stacks to couple the nodes between stack MOS devices to a supply voltage until their associated stack device changes logic state. On the changing state of the associated stack device, the node charging MOS device turns off, allowing the nodes to assume states defined by the input signals to the dynamic logic circuit.
摘要翻译： 描述用于消除MOS动态逻辑电路中的电荷共享噪声的电路。 具有控制限定电路的输出逻辑状态的公共节点的状态的MOS器件堆叠的动态逻辑电路容易受到电荷共享噪声的影响。 这种噪声最终来自公共节点必须提供的每个堆叠中的MOS器件之间的节点处的泄漏和杂散电容。 通过使用与堆叠中的MOS器件相关联的MOS器件来消除噪声，以将堆叠MOS器件之间的节点耦合到电源电压，直到其相关联的堆栈器件改变逻辑状态。 在相关联的堆叠设备的变化状态下，节点充电MOS器件关闭，允许节点采取由输入信号定义到动态逻辑电路的状态。
-
公开(公告)号：US06208907B1
公开(公告)日：2001-03-27
申请号：US09016653
申请日：1998-01-30
IPC分类号： G06F1900
CPC分类号： G06F9/38 , H03K19/0963 , H03K19/1735
摘要： A method and apparatus is provided for enabling the transformation of a domino circuit to a static circuit without requiring the re-design of the chip or integrated circuit mask set. The domino circuit masks may be designed to include additional unconnected devices as appropriate which may be added or connected into the circuit after chip design release by changing only interconnection masks. Spare devices can be added and selectively used to make a domino circuit metal-mask programmable into a logically equivalent static circuit. In a first exemplary method, extra devices are added to, and/or existing devices are re-wired in the domino circuitry to make a complementary equivalent static gate. In a second exemplary methodology, the domino circuit is converted into a pseudo-NMOS circuit using devices already available in the circuit and modifying the circuit connections thereto.
摘要翻译： 提供了一种方法和装置，用于使得能够将多米诺骨牌电路转换成静态电路，而不需要重新设计芯片或集成电路掩模组。 多米诺骨牌电路掩模可以被设计为包括适当的额外的未连接的设备，其可以通过仅改变互连掩模而在芯片设计释放之后被添加或连接到电路中。 备用器件可以添加并选择性地用于使多米诺骨电路金属掩模可编程成逻辑等效的静态电路。 在第一示例性方法中，添加额外的设备，和/或将现有设备重新连接在多米诺骨牌电路中以形成互补的等效静态门。 在第二示例性方法中，使用电路中已经可用的设备并修改其电路连接，将多米诺骨电路转换成伪NMOS电路。
-
6.发明授权Reduced power dynamic logic circuit that inhibits reevaluation of stable inputs 失效减少功率动态逻辑电路，抑制稳定输入的重新评估
公开(公告)号：US6037804A
公开(公告)日：2000-03-14
申请号：US049741
申请日：1998-03-27
申请人： Christopher McCall Durham , Visweswara Rao Kodali , Michael Ju Hyeok Lee , Douglas Ele Martin , Harsh Dev Sharma
发明人： Christopher McCall Durham , Visweswara Rao Kodali , Michael Ju Hyeok Lee , Douglas Ele Martin , Harsh Dev Sharma
IPC分类号： H03K19/00 , H03K19/096 , H03K19/094
CPC分类号： H03K19/096 , H03K19/0016
摘要： A reduced-power integrated circuit includes a circuit data input, a circuit data output, and at least one row of dynamic logic. The row of dynamic logic includes a row clock input, a row data input, and a row data output coupled to the circuit data output, where a value received at the row data input is derived from the value at the circuit data input. The integrated circuit further includes a comparator that compares current and previous values at the circuit data input and a switch that selectively sets the row clock signal received at the row clock input to an inactive state and temporarily maintains the row clock signal in the inactive state in response to the comparator detecting that the current previous values of at the circuit data input are equivalent. Consequently, the row of dynamic logic does not (and need not) reevaluate the circuit data input value, and power dissipation is reduced.
摘要翻译： 降低功率的集成电路包括电路数据输入，电路数据输出和至少一行动态逻辑。 动态逻辑行包括行时钟输入，行数据输入和耦合到电路数据输出的行数据输出，其中根据电路数据输入的值导出在行数据输入处接收的值。 集成电路还包括比较器，其比较电路数据输入端的当前值和先前值，以及开关，其选择性地将在行时钟输入处接收的行时钟信号设置为非活动状态，并将行时钟信号暂时保持在非活动状态 对比较器的响应检测到电路数据输入端的当前先前值是等效的。 因此，动态逻辑行（并不需要）重新评估电路数据输入值，并降低功耗。
-
公开(公告)号：US5852373A
公开(公告)日：1998-12-22
申请号：US723814
申请日：1996-09-30
IPC分类号： H03K19/0175 , H03K19/096 , H03K19/0948
CPC分类号： H03K19/0963
摘要： A dynamic logic circuit is capable of receiving both dynamic and static input signals during both the precharge and evaluate phases of the logic circuit, and the static input signal is permitted to switch from both a low level to a high level and a high level to a low level during such stages and the logic circuit is still capable of correctly evaluating the implemented logical operation on the static and dynamic input signals. This is performed in CMOS by coupling a PFET between the internal precharge node and a voltage reference source where the gate electrode of the PFET device receives the static input signal.
摘要翻译： 动态逻辑电路能够在逻辑电路的预充电和评估阶段期间接收动态和静态输入信号，并且静态输入信号被允许从低电平切换到高电平和高电平 在这种阶段期间的低电平，并且逻辑电路仍然能够正确评估对静态和动态输入信号的实现的逻辑运算。 这通过在内部预充电节点和PFET器件的栅电极接收静态输入信号的电压参考源之间耦合PFET来实现。
-
公开(公告)号：US6107852A
公开(公告)日：2000-08-22
申请号：US81001
申请日：1998-05-19
CPC分类号： H03K3/012 , H03K3/356156
摘要： A method and device are disclosed for the reduction of the penalty associated with inserting a latch in a circuit which is utilized to implement an integrated circuit in a data-processing system. A semiconductor device is disclosed which includes a main latch circuit, a feedback latch circuit and an output terminal. The main latch circuit is capable of receiving an input data signal and an input clock signal. The main latch circuit generates a latch output signal in response to the input data and clock signals. The feedback latch circuit is capable of receiving the latch output signal from the main latch circuit and storing the latch output signal. The feedback latch circuit is capable of generating a feedback latch circuit output signal which is received by the main latch circuit to maintain the latch output signal. The output terminal of the device is coupled to the feedback latch circuit for outputting a device output signal which is equal to the feedback latch circuit output signal.
摘要翻译： 公开了一种用于减少与用于在数据处理系统中实现集成电路的电路中插入锁存相关联的惩罚的方法和装置。 公开了一种半导体器件，其包括主锁存电路，反馈锁存电路和输出端子。 主锁存电路能够接收输入数据信号和输入时钟信号。 主锁存电路根据输入数据和时钟信号产生锁存输出信号。 反馈锁存电路能够接收来自主锁存电路的锁存输出信号并存储锁存器输出信号。 反馈锁存电路能够产生由主锁存电路接收的反馈锁存电路输出信号，以维持锁存输出信号。 设备的输出端耦合到反馈锁存电路，用于输出等于反馈锁存电路输出信号的器件输出信号。
-
公开(公告)号：US6094071A
公开(公告)日：2000-07-25
申请号：US270188
申请日：1999-03-15
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A system and method for initializing a threshold voltage level of a dynamic circuit prior to a transition of said dynamic circuit from a passive mode to an active mode. A dynamic logic circuit has a runtime operation that alternates between an active and a passive mode and includes at least one transistor having a floating body and a threshold voltage level. A switching device within the dynamic logic circuit forms a means from which the floating body draws an electric charge during the passive mode, thereby altering the threshold voltage level. The switching device receives a clock input signal during the dynamic circuit's active mode. Input selection means selectively replace the clock input signal with a pre-clock input signal into the switching device for a pre-determined period of time prior to a transition by the dynamic logic circuit from the passive mode to the active mode, such that the floating body may adequately discharge, thereby initializing the threshold voltage level prior to commencement of the active mode.
摘要翻译： 一种用于在将所述动态电路从被动模式转换到活动模式之前初始化动态电路的阈值电压电平的系统和方法。 动态逻辑电路具有在有源和无源模式之间交替的运行时间操作，并且包括具有浮动体和阈值电压电平的至少一个晶体管。 动态逻辑电路内的开关装置形成了在被动模式期间浮体从其吸取电荷的装置，从而改变阈值电压电平。 开关装置在动态电路的活动模式期间接收时钟输入信号。 输入选择意味着在将动态逻辑电路从被动模式转换到活动模式之前，将具有预时钟输入信号的时钟输入信号选择性地替换到开关装置中预定的时间段，使得浮置 主体可以充分地放电，从而在激活模式开始之前初始化阈值电压电平。
-
公开(公告)号：US6046606A
公开(公告)日：2000-04-04
申请号：US10200
申请日：1998-01-21
IPC分类号： H03K19/003 , G06F11/00 , H03K19/096 , H03K19/094 , H03K19/20
CPC分类号： G06F11/00 , G06F11/004
摘要： A method and apparatus is effective to preserve logic state potential levels in logic circuitry notwithstanding alpha particle collisions. Cross-coupled circuitry, including active devices, are implemented in a complementary logic circuit arrangement to hold current logic values in the event of a premature switching such as a switching that may be induced by alpha particle collision with the semiconductor logic circuit. Stabilizing transistor switching devices are arranged to sense an inappropriate or premature switching initiation and respond thereto by operating to maintain the appropriate logic levels within the logic circuitry. In one embodiment, the internal node of an upper circuit in a dual-rail logic circuit is connected to a gate terminal of a cross-coupled PFET device in the lower circuit. The cross-coupled PFET device is operable to sense an initiated untimely switching action in the upper circuit and effect a re-application of the holding PFET in the upper circuit to re-establish the appropriate logic potential levels in the upper circuit.
摘要翻译： 尽管存在α粒子碰撞，但是方法和装置有效地保持逻辑电路中的逻辑状态电位电平。 包括有源器件的交叉耦合电路在互补逻辑电路装置中实现，以在诸如可能由半导体逻辑电路的α粒子碰撞引起的切换的过早切换的情况下保持当前逻辑值。 稳定晶体管开关器件被布置为感测不适当或过早的开关启动，并通过操作来响应于其来维持逻辑电路内的适当的逻辑电平。 在一个实施例中，双轨逻辑电路中的上电路的内部节点连接到下电路中的交叉耦合PFET器件的栅极端子。 交叉耦合PFET器件可操作以感测上电路中引发的不合时宜的开关动作，并且实现上电路中保持PFET的重新施加，以重新建立上电路中适当的逻辑电位电平。
-
-
-
-
-
-
-
-
-
搜索结果
10 条记录 (耗时 0.014 秒)
