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1.发明授权公开(公告)号：US07635614B1
公开(公告)日：2009-12-22
申请号：US11724622
申请日：2007-03-15
IPC分类号： H01L21/323 , H01L29/74
CPC分类号： H01L29/7436 , H01L29/7404 , H01L29/749
摘要： An NLDMOS SCR device based on an LDMOS fabrication process includes a dual gate to provide controllable switching characteristics to allow it to be used for ESD protection of fast switching voltage regulators.
摘要翻译： 基于LDMOS制造工艺的NLDMOS SCR器件包括提供可控开关特性以允许其用于快速开关电压调节器的ESD保护的双栅极。
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2.发明授权ESD protection device with controllable triggering characteristics using driver circuit related to power supply 有权具有可控触发特性的ESD保护器件使用与电源相关的驱动电路公开(公告)号：US07800127B1
公开(公告)日：2010-09-21
申请号：US11503593
申请日：2006-08-14
IPC分类号： H01L23/62
CPC分类号： H01L29/7436 , H01L27/0262 , H01L29/87
摘要： In an ESD device for fast switching applications based on a BSCR or NLDMOS-SCR, an anode junction control electrode is provided by not connecting the anode electrode to the collector of the BSCR or to the drain of the NLDMOS-SCR, and a cathode junction control electrode is provided by forming an additional n+ region in the BSCR or an additional p+ region in the p-well of the NLDMOS-SCR. The triggering voltage of the ESD device is adjusted after a time delay by controlling one or both of the control electrodes using an RC-timer-driver circuit.
摘要翻译： 在用于基于BSCR或NLDMOS-SCR的快速切换应用的ESD装置中，阳极结控制电极通过不将阳极电极连接到BSCR的集电极或NLDMOS-SCR的漏极而提供，并且阴极结 通过在BSCR中的附加n +区域或NLDMOS-SCR的p阱中的附加p +区域形成控制电极。 通过使用RC定时器驱动器电路控制一个或两个控制电极，在延迟之后调整ESD装置的触发电压。
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公开(公告)号：US07795102B1
公开(公告)日：2010-09-14
申请号：US11654735
申请日：2007-01-17
IPC分类号： H01L21/331
CPC分类号： H01L29/8611 , H01L27/0255 , H01L29/161 , H01L29/66128
摘要： In a SiGe BJT process, a diode is formed by defining a p-n junction between the BJT collector and BJT internal base, blocking the external gate regions of the BJT and doping the emitter poly of the BJT with the same dopant type as the internal base thereby using the emitter contact to define the contact to the internal base. Electrical contact to the collector is established through a sub-collector or by means of a second emitter poly and internal base both doped with the same dopant type as the collector.
摘要翻译： 在SiGe BJT工艺中，通过限定BJT集电极和BJT内部基极之间的pn结，形成二极管，阻挡BJT的外部栅极区域，并以与内部基底相同的掺杂剂类型掺杂BJT的发射极多晶， 使用发射极接触来定义与内部基座的接触。 通过子集电极或通过掺杂与收集器相同的掺杂剂类型的第二发射极多晶硅和内部基极建立与集电极的电接触。
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公开(公告)号：US08497167B1
公开(公告)日：2013-07-30
申请号：US11654736
申请日：2007-01-17
IPC分类号： H01L31/107 , H01L23/60
CPC分类号： H01L27/0255 , H01L29/063 , H01L29/861
摘要： A high voltage ESD protection diode wherein the p-n junction is defined by a p-well and an n-well and includes a RESURF region, the diode including a field oxide layer formed on top of the p-well and n-well, wherein the parameters of the diode are adjustable by controlling one or more of the junction width, the length of the RESURF region, or the length of the field oxide layer.
摘要翻译： 一种高压ESD保护二极管，其中pn结由p阱和n阱限定并且包括RESURF区，所述二极管包括形成在p阱和n阱顶部的场氧化物层，其中， 通过控制一个或多个结宽度，RESURF区域的长度或场氧化物层的长度可以调节二极管的参数。
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公开(公告)号：US07973386B1
公开(公告)日：2011-07-05
申请号：US11652982
申请日：2007-01-12
IPC分类号： H01L29/66
CPC分类号： H01L29/866 , H01L27/0259 , H01L29/7375
摘要： In a bipolar device an intrinsic Zener like diode is formed for controlling the triggering voltage and leakage current, the Zener-like diode being formed between the n-collector and the p-base, wherein the collector implant and base diffusion overlap at least partially.
摘要翻译： 在双极器件中，形成内部齐纳二极管，用于控制触发电压和漏电流，齐纳二极管形成在n极集电极和p基极之间，其中集电极注入和基极扩散至少部分重叠。
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公开(公告)号：US08524548B2
公开(公告)日：2013-09-03
申请号：US13094645
申请日：2011-04-26
申请人： William French , Vladislav Vashchenko , Richard Wendell Foote, Jr. , Alexei Sadovnikov , Punit Bhola , Peter J. Hopper
发明人： William French , Vladislav Vashchenko , Richard Wendell Foote, Jr. , Alexei Sadovnikov , Punit Bhola , Peter J. Hopper
IPC分类号： H01L29/66
CPC分类号： H01L29/7824 , H01L21/26586 , H01L29/0653 , H01L29/0878 , H01L29/1095 , H01L29/66689 , H01L29/7835 , H01L29/78603
摘要： A lateral DMOS transistor formed on a silicon-on-insulator (SOI) structure has a higher breakdown voltage that results from a cavity that is formed in the bulk region of the SOI structure. The cavity exposes a portion of the bottom surface of the insulator layer of the SOI structure that lies directly vertically below the drift region of the DMOS transistor.
摘要翻译： 形成在绝缘体上硅（SOI）结构上的横向DMOS晶体具有较高的击穿电压，该击穿电压是由在SOI结构的体区形成的空穴产生的。 空腔暴露SOI结构的绝缘体层的底部表面的一部分，其直接位于DMOS晶体管的漂移区的垂直下方。
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公开(公告)号：US07795047B1
公开(公告)日：2010-09-14
申请号：US11016010
申请日：2004-12-17
IPC分类号： H01L31/072
CPC分类号： H01L29/7322 , H01L27/0259 , H01L29/0813
摘要： In a method and structure for current balancing the emitter current in a multi-finger n-emitter of a BJT or BSCR, back-end or polysilicon resistors are applied between the emitter fingers and the power rail, with the resistors chosen to be larger the closer the emitter fingers are to the collector.
摘要翻译： 在用于电流平衡BJT或BSCR的多指n发射极中的发射极电流的方法和结构中，后端或多晶硅电阻器被施加在发射极和电源轨之间，其中电阻器选择为大于 发射器手指靠近收集器。
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8.发明授权ESD clamps and NMOS arrays with increased electrical overstress robustness 有权ESD钳位和NMOS阵列具有增加的电应力坚固性公开(公告)号：US07718480B1
公开(公告)日：2010-05-18
申请号：US11138221
申请日：2005-05-26
IPC分类号： H01L21/00
CPC分类号： H01L27/0266 , H01L29/0692 , H01L29/1045 , H01L29/1087 , H01L29/78
摘要： In an NMOS active clamp device and an NMOS active clamp array with multiple source and drain contacts, the robustness against ESD events is increased by reducing channel resistance through the inclusion of one or more p+ regions formed at least partially in the source and electrically connected to the one or more source contacts.
摘要翻译： 在具有多个源极和漏极触点的NMOS有源钳位装置和NMOS有源钳位阵列中，通过包括至少部分地形成在源极中的一个或多个p +区域并且电连接到 一个或多个源接触。
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公开(公告)号：US07639464B1
公开(公告)日：2009-12-29
申请号：US11376492
申请日：2006-03-15
CPC分类号： H01L27/0266
摘要： In a dual direction ESD protection structure, first and second NMOS devices are serially connected back-to-back by connecting their drains or their sources using a common floating interconnect, while ensuring that the devices remain isolated from each other.
摘要翻译： 在双向ESD保护结构中，第一和第二NMOS器件通过使用公共浮动互连连接它们的漏极或其源极而被背对背地串联连接，同时确保器件保持彼此隔离。
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公开(公告)号：US20090162978A1
公开(公告)日：2009-06-25
申请号：US12395506
申请日：2009-02-27
IPC分类号： H01L21/332
CPC分类号： H01L27/0259
摘要： A diode for alternating current (DIAC) electrostatic discharge (ESD) protection circuit is formed in a silicon germanium (SiGe) hetrojunction bipolar transistor (HBT) process that utilizes a very thin collector region. ESD protection for a pair of to-be-protected pads is provided by utilizing the base structures and the emitter structures of the SiGe transistors.
摘要翻译： 用于交流（DIAC）静电放电（ESD）保护电路的二极管形成在利用非常薄的集电极区域的硅锗（SiGe）合金双极晶体管（HBT）工艺中。 通过利用SiGe晶体管的基极结构和发射极结构，提供一对待保护焊盘的ESD保护。
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